From the White-Haired Stock God to the Billion-Dollar Fund Titan: The Smart People Shorting NVIDIA Are Getting Rich Using the Same Framework

链捕手發佈於 2026-06-26更新於 2026-06-26

文章摘要

From "white-haired stock god" to billionaire fund manager, those profiting from shorting NVIDIA share a common framework. The article analyzes the critical bottlenecks in the AI hardware supply chain, which have become key investment focal points. The core argument is that the real constraint on the AI boom isn't software or algorithms, but fundamental physical infrastructure. The piece dissects nine major bottlenecks, organized around the lifecycle of an AI accelerator circuit board. *Before the Board*: The pre-manufacturing stage faces constraints in EDA tools, new materials (like GaN, SiC, InP) replacing silicon, and the critical, non-renewable supply of helium for semiconductor fabrication. *On the Board*: The primary bottlenecks are High-Bandwidth Memory (HBM), essential for unleashing GPU power, and advanced packaging (e.g., CoWoS), required to integrate components. Both are in severe shortage. *Between Boards*: Chip-to-chip communication is hitting limits with copper, pushing photonics and optical interconnects (CPO) as the next-gen solution, with NVIDIA heavily investing in this area. *Around the Board*: Power delivery requires new materials (GaN/SiC) for efficient voltage conversion from 48V to sub-1V. High-density AI racks (120kW+) are forcing a shift from air to liquid cooling as the standard. *Beyond the Board*: The ultimate bottleneck is electricity. AI data centers consume power equivalent to mid-sized cities, and grid expansion lags far behind demand, cau...

Leopold started a fund with $225 million, grew it to $5.5 billion in 12 months, and has now expanded it to $13 billion. He bets on the bottlenecks: power, computing power, memory, optical interconnect—the physical infrastructure of AI.

His portfolio doesn't hold a single share of NVIDIA. Instead, he uses $8.46 billion worth of put options to short the entire chip sector.

The 'White-Haired Stock God' who rejected NVIDIA's offer when its stock was at $6, picks small-cap stocks with his 'Perilla Leaf Theory,' and claims a 225x annualized return. He bets on bottlenecks like CPO optical interconnect, InP substrates, and optical transceivers—the upstream AI optical communication supply chain.

Intel CEO Lip-Bu Tan further emphasized this theory in an interview on the No Priors podcast on June 18, 2026. Before taking the helm at Intel, Tan served as CEO of Cadence for twelve years, during which its stock price multiplied by 32x.

He is also one of the most active venture capitalists in the semiconductor field, having personally invested in over 200 semiconductor companies, with 159 of them going public. His bets cover bottlenecks like EDA, new materials (GaN/SiC/InP), and optical interconnect.

One Circuit Board, the Entire AI Hardware Supply Chain Unveiled

Pick up any AI accelerator circuit board.

Before it is manufactured, designers need EDA tools to validate the layout of tens of billions of transistors, use new materials like InP, GaN, SiC to replace silicon that is hitting physical limits, and use helium gas to protect every precise step in lithography and etching.

On the board, GPU chips and HBM memory are stacked together, connected via TSMC's CoWoS or Intel's EMIB through advanced packaging. The GPU determines the upper limit of computing power, HBM determines whether that power can be unleashed, and packaging determines whether they can be assembled together.

Between boards, thousands of such accelerators need to work in sync. Copper cables are nearing their physical bandwidth limits, and optical interconnect is taking over.

Around the board, 48V voltage needs to be stepped down to the less than 1V required by the GPU, with each conversion generating heat; a rack with a power consumption of 120kW can no longer be cooled by traditional air cooling, making liquid cooling the new standard.

Beyond the board, all of this requires electricity. The power consumption of one AI data center equals that of a medium-sized city, while grid expansion and new power generation facilities take years to build.

This is the complete picture of the nine bottlenecks. Let's break them down one by one.

Before the Board

EDA: One Tape-Out Failure, Tens of Millions Lost

All chips must be designed and verified using EDA before manufacturing, with verification accounting for 60%-70% of the entire chip development cycle.

AI accelerators integrate hundreds of billions of transistors, compounded by HBM, 3D stacking, and advanced packaging, which continuously amplifies design complexity. However, the computational efficiency of EDA tools hasn't kept pace. If verification reveals issues requiring a re-spin, the failure cost can exceed tens of millions of dollars.

The EDA market size in 2025 was about $14.5 billion, projected to approach $18 billion in 2026. Synopsys, Cadence, and Siemens together capture over 65% market share. Having served as Cadence CEO for twelve years, Lip-Bu Tan understands the pricing power in this segment better than most investors. He describes EDA as a gold mine. Cadence has already improved design convergence speed by 5x, and Siemens' AI systems achieve up to 10x acceleration in certain tasks.

New Materials: Silicon Can't Hold, Five Materials Step In

Traditional silicon-based materials are gradually hitting performance ceilings in power consumption, heat dissipation, and optical communication. Five new materials are becoming breakthroughs: GaN (high-frequency power devices), SiC (high-voltage, high-current), InP (optical communication), synthetic diamond (thermal conductivity), and glass substrates (advanced packaging).

800G and 1.6T optical modules rely on InP material, with a current demand gap of about 40%-60% for AI optical interconnect. Glass substrates are seen as the next direction for advanced packaging, with both Intel and TSMC accelerating production. Wolfspeed and Infineon alone are investing over $15 billion in SiC capacity from 2025 to 2027.

Helium: Non-Renewable, Supply Disruption Means Production Halt

Early 2026, an event most investors completely missed: supply disruptions at Qatar's Ras Laffan affected 27%-30% of global helium supply, spot prices spiked 40%-100% short-term. South Korea's semiconductor industry relies on Qatari helium for about 64.7%, putting Samsung's and SK Hynix's HBM production lines at supply risk.

Helium is used throughout EUV lithography, etching, deposition, wafer cooling, etc. It is non-renewable and has no substitute. The semiconductor industry consumes about 24% of global helium, expected to rise to 30% by 2030. Worse, 2nm processes consume about 20% more helium per unit than 3nm. The more advanced the process, the more dependent it is on a resource that is dwindling.

Samsung has introduced a helium recycling system; TSMC's advanced production lines achieve 80%-90% recovery rates. But recycling can only alleviate, not solve, the fundamental problem: supply is concentrated in few locations, new source development takes years.

On the Board

HBM: Supply-Demand Mismatch, DRAM Prices Doubled in Two Years

HBM provides high-speed data transfer capabilities for GPUs, supply remains chronically tight and has become a core bottleneck limiting AI server shipments. Memory is the most scarce resource of all.

Global HBM market size is projected to be about $9.2 billion in 2026, potentially growing to nearly $70 billion by 2035, with a CAGR exceeding 25%. SK Hynix, Samsung, and Micron dominate the market. SK Hynix, with leading capacity, is NVIDIA's core supplier; Samsung and Micron are accelerating production of HBM3E and HBM4.

GPU sets the computing power ceiling; HBM determines if that power can be unleashed.

Advanced Packaging: GPUs Are Made, But Can't Get Packaged

Advanced packaging integrates GPU and HBM into a complete AI accelerator; TSMC's CoWoS is the mainstream solution. Even after GPUs and HBM are produced, they cannot be turned into computing power without packaging.

TSMC's CEO publicly stated CoWoS capacity is "extremely tight, sold out for 2026". Capacity has increased from about 35k-40k wafers/month at end-2024 to a target of 120k-140k wafers/month in 2026, but demand is growing faster. Global CoWoS demand in 2026 is projected near 1 million wafers, with NVIDIA alone accounting for about 60% and locking down significant capacity via long-term contracts.

Intel is betting on EMIB and glass substrate solutions to compete with TSMC in packaging; ASE, Amkor, and other packaging houses are also expanding capacity.

Between Boards

Interconnect/Photonics: Copper Cables Can't Keep Up, Optics Takes Over

Training large models requires thousands or even tens of thousands of GPUs working together. No matter how powerful a single GPU is, if inter-chip data transfer speeds can't keep up, the actual utilization of the entire cluster is dragged down. Mainstream copper cable interconnect is approaching its physical bandwidth limit, making high-speed interconnect chips and new interconnect architectures a focus of heavy capital investment.

Photonics is the next-generation solution for the interconnect bottleneck. Electrical signals suffer from attenuation and heating over long distances and in high-density scenarios, whereas optical signals have physical advantages. Silicon photonics and CPO (Co-Packaged Optics) could reduce interconnect power consumption by 30%-50%, but manufacturing processes, packaging integration, and cost control are not yet mature, creating a clear gap between capacity and AI cluster demand. The optical interconnect market in 2025 was about $15 billion, potentially reaching $43 billion by 2034.

Jensen Huang has invested in almost all companies working on optical interconnect.Since 2026, NVIDIA has invested over $6.5 billion in photonics: about $2 billion each in Lumentum and Coherent, and $500 million in Ayar Labs for silicon photonics.

Around the Board

Power Conversion: Stepping 48V Down to 1V, Traditional Silicon Can't Handle It

AI servers need to step down 48V or higher voltages to the less than 1V required for GPU operation through multiple stages of conversion. Traditional silicon-based power devices are inefficient in high-power scenarios; GaN and SiC are becoming the next-generation solutions.

According to onsemi estimates, the value of power semiconductors in a next-gen 1MW AI rack doubles from about $50k to $100k. The GaN/SiC power device market in 2025-2026 is about $2 billion, projected to exceed $8 billion by 2030, with a CAGR over 20%.

Infineon acquired GaN Systems to complete its product line; Navitas launched GaN power solutions for AI data centers; onsemi, Wolfspeed, STMicroelectronics are also accelerating SiC capacity expansion.

Liquid Cooling: One Rack at 120kW, Air Cooling Can't Cope

Represented by NVIDIA's GB200 NVL72, next-gen AI server racks consume over 120kW. Cooling this heat with just fans would require excessive space and create unacceptable noise levels. Liquid cooling is becoming the standard for next-generation AI data centers.

The global data center liquid cooling market in 2025 was about $5 billion, potentially growing to $27.1 billion by 2035. Adoption rate of liquid cooling in new AI data centers is projected to rise from about 35% in 2025 to about 55% by end-2026.

NVIDIA promotes liquid cooling architecture in its Blackwell and Rubin platforms; Microsoft, Google, Amazon, Meta are accelerating adoption in new data centers. For chip-level cooling, Lip-Bu Tan has invested in synthetic diamond, leveraging its high thermal conductivity to address localized heat concentration in high-power chips.

Beyond the Board

Power: Grid Can't Keep Up, Data Centers Queue for Electricity

In the US, numerous data center projects already face delays due to insufficient grid access.

Combined 2026 capital expenditure for Amazon, Microsoft, Google, Meta is projected at $700 billion, a significant portion flowing to AI infrastructure and energy support. Traditional grid expansion can't keep pace, leading tech companies to turn to long-term power purchase agreements, natural gas, and nuclear power alternatives.

Leopold believes a behind-the-scenes war is underway in Silicon Valley to secure all remaining power contracts and every transformer for the rest of the century. His judgment: the real bottleneck of the AI era is not algorithms, but electricity.

Williams invested $5.1 billion in modular natural gas power facilities; GE Vernova's gas turbine order backlog reached 100GW level; NVIDIA invested in TerraPower via NVentures to promote small modular reactors; the Stargate project is also exploring nuclear power.

Compared to other tech bottlenecks, power infrastructure involves grids, land, approvals, has longer build cycles, and is harder to replicate quickly.

How Long Will This Framework Work

How long can this bottleneck investment framework last? It depends on when supply catches up with demand.

Judging by capacity build-out timelines, the second half of 2027 is the first supply release point: SK Hynix's M15X plant is scheduled for mid-2027 production; Micron's Singapore and Taiwan plants also target 2027. The White-Haired Stock God predicts the photonics supercycle will also start ramping up around mid-2027. 2028 is the second wave: Samsung's Pyeongtaek P5 plant, SK Hynix's Indiana plant, and Micron's Hiroshima plant come online. Lip-Bu Tan's judgment: "No relief before 2028."

But new capacity coming online doesn't mean bottlenecks disappear. Each generation of GPU roughly doubles HBM demand; NVIDIA's next-gen Rubin architecture will further amplify demand for HBM4. Moreover, hyperscalers have already locked down a significant portion of new capacity via long-term contracts, leaving limited shares for the open market.

In 2017-2018, DRAM prices surged, Samsung drastically expanded production, capital expenditure increased over 50%. After new capacity flooded the market in 2019, prices crashed, causing industry-wide losses. From capacity investment to price reversal, it took 18 months.

This cycle is far larger. DRAM prices from 2025 to 2027 are projected to rise about 275%-300%, three times the increase of 2017-2018, on a revenue base three times larger. SK Hynix, Samsung, and Micron all have market caps exceeding $1 trillion. HBM boasts gross margins of 60%-70%, far exceeding traditional DRAM. If we extrapolate using the same 18-month window, late 2028 to mid-2029 is the period to be highly vigilant.

The real signal to watch: if AI capex growth slows by then, while new capacity from the three giants comes online simultaneously, the supply-demand balance could reverse rapidly, turning bottlenecks into gluts, shifting pricing power from suppliers back to buyers.

Leopold's moves suggest he's already preparing for this scenario. While going long on power and infrastructure, he holds $8.46 billion in put options shorting the semiconductor sector. His judgment: once the AI infrastructure build-out cycle peaks, fierce competition among chipmakers will compress margins, but the scarcity of power and physical infrastructure is more enduring and harder to replicate.

Until then, the supply-demand imbalance in this chain shows no sign of easing.

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相關問答

QAccording to the article, what is the core investment framework shared by the profiled investors (Leopold, 'White-haired Stock God', Chen Lifa), and what do they invest in?

AThe core investment framework is identifying and investing in the physical bottlenecks constraining the development of AI infrastructure. They specifically target areas where supply struggles to meet explosive demand. Their investments are concentrated in: EDA tools, new materials (GaN, SiC, InP, glass substrates, artificial diamond), helium, HBM memory, advanced packaging (CoWoS, EMIB), optical/photonic interconnects, power conversion (GaN/SiC), liquid cooling, and the foundational electricity/power infrastructure.

QWhy does Leopold hold a significant ($8.46B) short position (via put options) against the chip sector while also investing heavily in AI bottlenecks?

ALeopold holds this short position as a hedge against a future market reversal. His strategy is to profit from the current supply bottlenecks but also prepare for a scenario where massive new chip and HBM manufacturing capacity comes online around 2028-2029. He believes that if AI capital expenditure growth slows at that time while supply surges, the chip sector could face a supply glut and profit margin compression. He contrasts this with physical infrastructure like electricity, which he views as having more persistent, long-term scarcity.

QBased on the article, what are the key bottlenecks 'On the Board' of an AI accelerator, and why are they critical?

AThe key bottlenecks on the board are HBM (High Bandwidth Memory) and Advanced Packaging. HBM is critical because it provides the high-speed data transfer capability for the GPU; a powerful GPU is limited if memory cannot feed it data fast enough. Advanced Packaging (e.g., TSMC's CoWoS) is critical because it integrates the GPU and HBM into a functional unit. Even if both components are manufactured, the inability to package them together creates a major production bottleneck, preventing the creation of complete AI accelerators.

QWhat future event does the article suggest could signal the end of the current 'bottleneck' investment cycle, and what historical precedent is cited?

AThe article suggests the cycle could end when AI capital expenditure growth slows while the massive new manufacturing capacity (from SK Hynix, Samsung, and Micron) planned for 2027-2028 comes online simultaneously, potentially flipping the market from shortage to surplus. The historical precedent cited is the 2017-2018 DRAM price boom and subsequent bust. After Samsung and others aggressively expanded capacity, a glut emerged about 18 months later in 2019, causing prices to crash and industry-wide losses. A similar pattern is predicted, but on a much larger scale, with a potential turning point around late 2028 to mid-2029.

QHow does the article characterize the electricity/power challenge for AI data centers, and why is it considered a uniquely difficult bottleneck?

AThe article characterizes electricity as the ultimate bottleneck for AI, stating that a single AI data center can consume as much power as a medium-sized city. The challenge is that traditional power grid expansion cannot keep pace with the explosive demand from tech giants' AI infrastructure projects. It is considered uniquely difficult because, unlike other technical bottlenecks, solving the power constraint involves lengthy processes like grid upgrades, land acquisition, regulatory approvals, and building new power generation facilities (natural gas plants, small modular nuclear reactors), which have much longer construction cycles and are harder to rapidly scale or replicate.

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