Two-dimensional (2D) semiconductors, also known as atomic layer semiconductors, are semiconductor materials whose core functional layers are only a single or a few atomic layers thick. Represented by transition metal dichalcogenides (e.g., molybdenum disulfide), they are among the key materials for the post-Moore era. As silicon-based chip manufacturing processes approach physical limits, traditional silicon channel semiconductor materials are nearing their performance ceiling. 2D semiconductors (such as MoS2, WSe2, InSe), leveraging their inherent advantage of atomic-level thickness, can achieve natural strong gate control at short-channel scales with wafer-scale atomically flat structures, and are regarded as the most promising non-silicon new material for the post-Moore era.
Currently, a global industrial consensus is rapidly forming. Leading international wafer manufacturing giants like TSMC, Intel, and Samsung, as well as top research institutions such as IMEC and IRDS, have all explicitly positioned themselves in the 2D semiconductor field, judging that they will be integrated as core components into heterogeneous integration systems after the 1nm node. In June 2026, TSMC, in collaboration with ASML and imec, demonstrated for the first time at the VLSI Symposium the integration of 2D n/pFETs with a 50 nm gate-contact pitch on a 300 mm wafer, signifying that international giants are accelerating the push for 2D transistors from lab to fab. In this context, the domestic industry chain has also accelerated full-chain layout, achieving breakthroughs from material preparation and equipment self-development to chip integration and ecosystem construction. The 2D semiconductor industry chain is taking shape.
01 Material Breakthroughs and Equipment Autonomy: From 'Can Make' to 'Can Produce'
2D semiconductors are considered key materials for post-silicon chip manufacturing, but the large-scale, high-quality wafer preparation of 2D semiconductor materials is a prerequisite for their industrial application. Among them, Chemical Vapor Deposition (CVD) and Metal-Organic Chemical Vapor Deposition (MOCVD) are key technologies for future large-scale manufacturing of 2D semiconductor materials.
In the field of equipment and material growth, a team led by Professor Wang Xinran from Nanjing University, in collaboration with its industrial transformation platform Jimoxin Technology, has formed a deep closed-loop integration of "academic innovation—equipment development—process verification," achieving a series of advancements in wafer-scale 2D semiconductor single-crystal preparation. In October 2025, leveraging the Oxy-MOCVD 200 ultra equipment (with 100% domestic core components) independently developed by Jimoxin Technology, and through innovative substrate engineering techniques, the team reported for the first time globally the mass-production preparation of the world's first 6-inch 2D transition metal dichalcogenide semiconductor single crystal, compatible with materials like MoS2, WS2, and WSe2, with a unidirectional domain alignment rate exceeding 99% on a 150 mm wafer. In January 2026, collaborating with Professor Wang Jinlan's team from Southeast University, they developed a novel Oxygen-assisted Metal-Organic Chemical Vapor Deposition (oxy-MOCVD) technology, breaking through the bottleneck of growth kinetics control. This not only increased the average domain size of MoS2 crystals from the hundred-nanometer scale to hundreds of micrometers, solving the mass-production challenge of large-area uniform growth, but also fundamentally suppressed carbon contamination issues. Based on this process, Jimoxin Technology completed in-depth customization and upgrades of its equipment, enabling plug-and-play process capabilities for downstream users. The current technology system covers mainstream 2D semiconductor materials like MoS2, MoSe2, WS2, and WSe2. Building on this, Jimoxin Technology has further achieved a global first by realizing mass production of 8-inch 2D semiconductor single crystals. Its products have entered top research institutions like the University of Cambridge and Fudan University, and collaborations have been established with downstream chip manufacturers, bridging the critical step from lab samples to production-grade materials.
Beyond mainstream n-type materials, the shortcoming in wafer-level preparation of p-type 2D semiconductors has also been addressed. Similar to silicon-based electronic devices, wafer-level n-type and p-type 2D semiconductor single crystals are the foundation and prerequisite for building 2D CMOS integrated circuits. To date, researchers have developed various n-type 2D semiconductor materials, among which MoS2 and WS2 have achieved wafer-scale single-crystal preparation. However, p-type 2D semiconductors combining high mobility and excellent stability remain scarce, and achieving wafer-level single-crystal growth of such materials is even more challenging. In July 2026, a team from the Institute of Metal Research, Chinese Academy of Sciences, made a breakthrough by successfully preparing large-area, high-performance p-type MoSi2N4 monolayer single-crystal wafers. This material system was pioneered by this team, previously only achievable as polycrystalline films where grain boundary gaps would significantly degrade device performance and cause damage during transfer processes. This research, through the step-guided effect of a special single-crystal substrate, achieved directional growth and seamless splicing of the material, finally filling the core gap of long-missing high-quality p-type materials for 2D CMOS circuits.
In the direction of specialty materials, a research team led by Professor Peng Hailin from Peking University achieved, for the first time, the controlled preparation of ultra-thin, uniform ferroelectric thin films and their heterostructures at the wafer scale. They constructed high-speed ferroelectric transistors with ultra-low operating voltage (0.8V) and extremely high endurance (surviving over 1.5×10^12 cycles). Their overall performance significantly surpasses existing industrial hafnium-based ferroelectric systems, representing the currently known ferroelectric transistor with the smallest operating voltage, lowest energy consumption, and best endurance. This marks the first international demonstration of a high-performance wafer-level 2D ferroelectric material system, providing a breakthrough material foundation and feasible technological pathway for developing high-efficiency advanced chips.
02 Engineering Ecosystem Gradually Forms, Bridging the Gap from Lab to Fab
Breakthroughs in materials and devices ultimately need to be integrated into standardized manufacturing systems.
On July 9, 2026, the 8-inch Two-Dimensional Semiconductor Engineering Demonstration Pilot Line, built by Yuanyiwei Technology, was fully operational in Pudong, becoming a milestone for China's 2D semiconductor transition from research to industrialization. This pilot line achieved first light in January 2026 and, in just over half a year, completed full-process equipment debugging and process optimization. Differentiating itself from small-scale lab trial platforms, it now possesses complete tape-out and engineering trial production capabilities, establishing a full engineering chain from material preparation to chip integration. Prior to this, domestic 2D semiconductor research was mostly concentrated in university labs, with device preparation relying on small-batch manual trials, leaving a significant gap from industrial standards. The Yuanyiwei team, after ten years of dedicated effort, has mastered the complete manufacturing process encompassing wafer growth, integration processes, device modeling, circuit design, and packaging/testing.
The accompanying Process Design Kit (PDK) has also been deployed, further bridging the gap between design and manufacturing. The PDK 0.1 version for 500 nm nodes based on the 8-inch pilot line, released by Yuanyiwei, is the first process IP in the 2D semiconductor field compatible with mainstream EDA toolchains. It includes a complete set of tools like Pcells, DRC, LVS, and PEX, with a process yield exceeding 99.99%. Various performance metrics break international records, basically approaching the level of silicon-based processes at equivalent nodes. In the future, it can support the design and wafer-level manufacturing of 2D circuits with up to 100,000 gates.
Accompanying the line's operation and PDK release, foundry services and the industrial ecosystem have been simultaneously launched. University teams from Peking University, Tsinghua University, Shanghai Jiao Tong University, Nanjing University, and others have completed R&D collaboration agreements with Yuanyiwei, officially opening wafer foundry services to the research community. Companies like Xi'an XianDao Institute and Shanghai 2D Star Technology have also formed strategic industry chain partnerships, engaging in deep collaboration around shared process platforms, technology transfer, and ecosystem co-construction. Local industrial support is also advancing in sync. Shanghai Chuansha New Town is leveraging the Yuanyiwei pilot line as a core carrier to attract upstream and downstream companies. At the Shanghai municipal level, 2D semiconductors have been incorporated as a key cultivation direction for future industries, with comprehensive efforts from R&D and collaborative innovation to ecosystem nurturing, aiming to form a complete industrial loop of "R&D—Pilot—Mass Production." Notably, approximately 70% of the equipment for a 2D semiconductor production line can be reused from existing silicon-based semiconductor equipment, meaning it will not overturn the existing industrial system. Instead, it will foster entirely new market increments in areas like materials, equipment, manufacturing, and advanced packaging.
03 Expanding Application Landscape: From Computing to Storage
With the maturation of the manufacturing system, 2D semiconductors are also expanding from logic computing to application scenarios like storage.
In the logic computing domain, China has completed the leap from devices to complex processors. In 2025, the world's first 32-bit RISC-V architecture microprocessor based on 2D semiconductor materials, named "Wuji," was released. It employs molybdenum disulfide (MoS2) material, integrates 5900 transistors, is only 0.7 nm thick, and achieves a single-stage inverter yield of 99.77%, realizing full-chain independent R&D from material and architecture to tape-out, verifying the feasibility of building complex logic circuits with 2D materials. This processor can serially execute 37 types of 32-bit RISC-V instructions at a 1kHz clock frequency, meeting the RV32I integer instruction set requirements. It features high single-stage gain and ultra-low off-state leakage current, suitable for scenarios like IoT and edge computing.
In 2026, teams led by Professors Wang Xinran and Qiu Hao from Nanjing University, in collaboration with Suzhou National Laboratory and Huawei, further integrated the full design-process-manufacturing flow for 2D semiconductor chips compatible with Fab production lines. They successfully developed the world's first MoS2 multi-bit parallel microprocessor, "Mengqi (MAGIC)-1000," setting a new record for transistor integration density in emerging non-silicon digital circuits. This marks China's entry into a new development stage of production line integration in 2D semiconductor research. Through cross-level co-optimization, the team integrated 1433 MoS2 transistors into an ultra-compact chip area using a 0.5μm industrial process, successfully developing the "MAGIC-1000" microprocessor. The chip employs a RISC instruction set and consists of four main modules: instruction decoder, register file, arithmetic logic unit, and multiplexer. Its integrated transistor density increased by an order of magnitude compared to the previous international record, reaching 9336/mm², comparable to mature silicon-based processes at the same node. The chip achieved multi-bit data parallel operation with 2D semiconductors for the first time, with a maximum operating frequency of 43 kHz. It also integrated an on-chip register file on the 2D chip, eliminating the access latency and bandwidth bottlenecks associated with off-chip memory.
In the storage domain, the ultra-low leakage characteristics of 2D semiconductors demonstrate unique strategic value. A joint team from Fudan University developed the 2D semiconductor transistor with the lowest leakage current to date. The team achieved a record-breaking ultra-low leakage current—equivalent to leaking only one electron every 9.15 seconds. Building on this, they created a novel DRAM memory chip that achieved an ultra-long data retention time exceeding 8500 seconds at zero hold voltage, while simultaneously maintaining high-speed read/write and multi-capacity storage capabilities. The optimized Capacitorless Two-Transistor DRAM (2T0C) achieved quasi-non-volatile memory operation, 5-bit storage precision, and nanosecond-level write speeds. Yuanyiwei has positioned DRAM as a key strategic direction. The ultra-low leakage of 2D semiconductors can significantly reduce refresh power consumption, promising early adoption in edge-side and high-compute-power scenarios, with future capacity enhancement through 3D stacking technology. In July 2026, the team of Professors Zhou Peng and Liu Chunsen from Fudan University went a step further. For the first time, they clearly observed non-volatile single-electron storage behavior at room temperature, successfully creating a device with the world's largest non-volatile quantum storage window—requiring the injection of only a single electron to achieve a storage window of 0.5 volts. This signifies that charge information storage technology has reached the pinnacle of "one electron, one bit."
Beyond computing and storage, 2D semiconductors possess irreplaceable advantages in more specialized scenarios. As an ultimate SOI material, 2D semiconductors have unique advantages in radio frequency (RF) analog circuits, radiation-hardened communications, brain-computer interfaces, etc. In January of this year, relying on the "Fudan-1" satellite platform, a 2D semiconductor radiation-hardened RF communication system achieved its first in-orbit space validation. Additionally, 2D semiconductors can be fabricated into flexible, transparent devices, supporting device R&D in cutting-edge fields like optoelectronic sensing and quantum computing.
04 Conclusion
Currently, 2D semiconductors have completely moved out of the laboratory, entering a new development stage of engineering verification and small-batch tape-outs. From wafer-level breakthroughs in material preparation, to the engineering operation of manufacturing lines, to application deployment in multiple fields like computing and storage, every link in China's domestic 2D semiconductor industry chain is accelerating. An initial complete industry chain covering materials, equipment, manufacturing, design, and application has taken shape.
In this emerging 2D semiconductor field, international competition is in full swing. The formation of this new industry chain not only provides new possibilities for chip technology in the post-Moore era but also opens a brand-new dimension of competition in the reshaping of the global semiconductor industry landscape.
This article is from the WeChat public account "Semiconductor Industry Review" (ID: ICViews), author: Peng Cheng
