The Tao (τ) Law Makes EDA Go Viral
In May 2026, Huawei's semiconductor division introduced the "Tao (τ) Law" at IEEE ISCAS, shifting the industry focus from Moore's Law's geometric scaling to "time scaling." Unlike traditional approaches relying on transistor miniaturization, τ Law optimizes the time constant (τ) across device, circuit, chip, and system levels to improve information processing speed and efficiency. Huawei has already applied this principle, mass-producing 381 chips across various applications, with a target to achieve performance equivalent to 1.4nm technology by 2031.
The implementation of τ Law, involving techniques like Chiplet, 3DIC, and Logic Folding, places new demands on EDA tools, highlighting gaps in current offerings. Traditional 2D or pseudo-3D EDA flows lack native support for true 3D design, cross-layer co-optimization (STCO), and coupled multi-physics analysis (thermal, power, stress), which are crucial for advanced integration.
Chinese EDA companies, such as Empyrean Software, Primarius Technologies, and Xpeedic, are evolving from point-tool specialists to providing full-flow, system-level solutions. For instance, Peking University has developed a prototype "true 3D" EDA tool showing significant improvements in wirelength and timing. Empyrean Software has also launched a comprehensive 3DIC design and verification platform. The τ Law framework presents an opportunity for the domestic EDA industry to transition from achieving basic functionality to developing robust, integrated toolsets essential for next-generation chip design.
marsbit06/12 13:39
