# Advanced Packaging Articoli collegati

Il Centro Notizie HTX fornisce gli articoli più recenti e le analisi più approfondite su "Advanced Packaging", coprendo tendenze di mercato, aggiornamenti sui progetti, sviluppi tecnologici e politiche normative nel settore crypto.

Standing in the Light: A Comprehensive Guide to the Optical Module and CPO Supply Chain

"Standing in the Light: Understanding the Optical Module and CPO Industry Chain" This article analyzes the critical role of optical communication technology, specifically optical modules and Co-Packaged Optics (CPO), as the "nervous system" for modern AI data centers. With exponential growth in AI computational demands (e.g., NVIDIA's Vera Rubin architecture), traditional electrical interconnects using copper cables face severe bottlenecks in bandwidth, power consumption, and signal integrity over distance. The core function of an optical module is to act as a "translator," converting electrical signals from chips into optical signals for transmission over fiber (and vice-versa). Key internal components include lasers, modulators, photodetectors, drivers, and DSP chips. The industry is currently transitioning from 800G to 1.6T modules. However, the future lies in CPO. This next-generation technology integrates the optical engine directly with the switch ASIC/XPU on the same package substrate, drastically reducing power consumption (by ~3.5x according to NVIDIA), overcoming bandwidth density limits, and minimizing signal attenuation compared to traditional pluggable modules. Key challenges for CPO include advanced packaging capacity (dominated by TSMC), thermal management, repairability, and standardization. The article details the broader technology landscape, including Near-Packaged Optics (NPO, a pragmatic intermediate step), Linear-drive Pluggable Optics (LPO), Optical I/O (OIO for chip-level integration), and Optical Circuit Switches (OCS). A comprehensive CPO industry chain is mapped, highlighting shifting power dynamics: * **Architecture Definers:** NVIDIA, Broadcom, and Marvell now hold greater influence. * **Advanced Packaging & Manufacturing:** TSMC is central; Fabrinet is a key EMS player. * **Lasers ("The Heart"):** A strategic bottleneck. EML lasers are led by Lumentum and Coherent (both receiving major NVIDIA investments). CW lasers, favored for CPO/silicon photonics, see strong Chinese players like Source Photonics and Sicoya. * **Silicon Photonics Chips:** The mainstream path for CPO engines, with key players like Broadcom, Intel, Marvell, and China's Accelink. * **Fiber Connectivity Components:** A major new, high-growth market created by CPO, including Fiber Array Units (FAU), Polarization-Maintaining Fiber (PMF), and MPO connectors. Companies like Tianfu Communication and US Conec are leaders. * **Fiber & Cable:** Experiencing a super-cycle (e.g., Corning, Yangtze Optical Fiber). * **PCB/Substrates:** Requiring advanced materials (e.g., Shengyi Tech). * **DSP & SerDes:** Functions are integrated into switch ASICs in the CPO era (e.g., Broadcom, Astera Labs). * **Optical Module Makers:** Transitioning from standalone module suppliers to providers of optical engines and NPO/LPO solutions while riding the current pluggable boom (e.g., Zhongji Innolight, Eoptolink). The investment timeline is segmented: Short-term (2026-2027) features the "last feast" for pluggable modules and CPO's initial rollout. Medium-term (2027-2029) will see CPO expand and NPO peak. Long-term (2029-2032+) involves CPO/OIO penetration into intra-rack scaling. In conclusion, optical interconnects are fundamental to AI infrastructure. The competitive landscape sees US firms leading in architecture and high-end chips, TSMC in advanced packaging, and Chinese firms holding strong positions in modules, connectivity components, CW lasers, and fiber/cable. The future belongs to companies that can navigate the technological shift from "selling shovels" (modules) to "building highways" (CPO/OIO infrastructure).

marsbitIeri 10:10

Standing in the Light: A Comprehensive Guide to the Optical Module and CPO Supply Chain

marsbitIeri 10:10

Huawei's "Tao Law": A Comprehensive Overview of Core Companies

Huawei's "Tau Law": Core Companies Overview On May 25, 2026, Huawei's Director and President of the Semiconductor Business Division, He Tingbo, formally introduced the "Tau (τ) Law" at ISCAS 2026, marking a significant principle guiding industry development in the global semiconductor field from China. The Tau Law shifts focus from traditional Moore's Law, which pursues geometric transistor scaling, to "time scaling"—continuously compressing signal propagation delay (time constant τ) without solely relying on extreme feature size reduction. The core implementation path is "logic folding." This technique transforms circuit layouts from two-dimensional planes to multi-layer 3D stacks, using short vertical interconnects to replace long horizontal wiring, thereby drastically reducing τ. Huawei has already designed and mass-produced 381 chips following this principle over the past six years, with plans to launch a Kirin chip utilizing logic folding in Fall 2026. By 2031, high-end chips based on the Tau Law are expected to achieve performance levels equivalent to a 1.4nm process node. This development impacts several key industry segments, with related Chinese companies poised to benefit: 1. **EDA Design Software**: Essential for circuit-level optimization. Key players include: * **Empyrean Technology** (Huada Jiutian): China's largest full-flow EDA provider. * **Primarius Technologies** (Gailun Dianzi): Specializes in device modeling and verification. * **Semitronix** (Guangliwei): Focuses on yield enhancement and test chip EDA. 2. **Chiplet & Advanced Packaging**: Logic folding's 3D stacking necessitates advanced packaging (e.g., TSV, hybrid bonding). Core participants are: * **Tongfu Microelectronics**: A leader in advanced packaging and a key partner for AMD's Chiplet products. * **JCET Group** (Changdian Keji) & **Tianshui Huatian Technology**: Major OSATs with advanced packaging capabilities. * **VeriSilicon** (Xinyuan Gufen): Provides Chiplet-based design platforms and IP. 3. **Foundry Manufacturing**: Optimization must be implemented in transistor structures and process parameters. Potential foundries for Huawei's future chips include: * **SMIC**: China's leading foundry with advanced FinFET capabilities, the most likely candidate for next-gen Kirin chips. * **Hua Hong Semiconductor** (Huahong Gongsi): A leader in specialty processes (power, embedded memory). * **Nexchip Semiconductor** (Jinghe Jicheng): Major foundry for display driver ICs and MCUs. The Tau Law represents a strategic move towards architectural innovation and design-process co-optimization, driving demand across the domestic semiconductor supply chain.

marsbit05/25 11:33

Huawei's "Tao Law": A Comprehensive Overview of Core Companies

marsbit05/25 11:33

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