Author: Tide Research
In the field of semiconductor reverse engineering, TechInsights had dominated for decades. Last weekend, Dylan Patel's SemiAnalysis officially released the first public teardown report from its STEEL lab (Teardown Engineering & Evaluation Lab), targeting one of the world's most-watched chips: the Kirin 9030 Pro, manufactured on SMIC's most advanced N+3 process, which powers the Huawei Mate 80 Pro.
The timing is intriguing. While TechInsights is being sold by private equity, SemiAnalysis' revenue has already surpassed that of this established giant. Dylan chose this moment to demonstrate its capabilities with a technically dense teardown report, complemented by real chip photos from its Oregon lab.
The report's headline is a bombshell: SMIC's N+3 process features a minimum metal pitch (M0 pitch) of only 32.5nm, smaller than the 36nm pitch of Intel's latest Panther Lake processors using the 18A process.
SMIC, without EUV lithography machines, achieved a finer metal pitch than Intel?
On its own, this headline could send shockwaves through the semiconductor industry. However, SemiAnalysis itself pours cold water on it in the report's second paragraph, calling it a "cherry picked metric."
This article will interpret this teardown report for you.
Catching Up in Density, at a High Cost
SMIC's N+3 process has indeed caught up with TSMC's N6 in terms of transistor density.
Through TEM (Transmission Electron Microscopy) cross-sectional analysis, STEEL Lab measured the Bohr density of N+3 at 113.4 MTr/mm², slightly higher than TSMC N6's 107.7 MTr/mm². The cell height shrank from 252nm in N+2 to 228nm, and the contacted gate pitch (CGP) reduced from 63nm to 57nm. Taken together, these numbers mean that SMIC, using pure DUV lithography without EUV, has achieved logic density comparable to TSMC's mature 7nm-class processes.
At what cost?
SMIC's M0 layer uses Self-Aligned Quadruple Patterning (SAQP), where a single photomask pattern undergoes four processing steps to achieve finer lines. TSMC's N6 requires only Double Patterning (SADP) for the same layer. Quadruple patterning means more mask counts, stricter overlay accuracy requirements, more complex process flows, and higher costs.
SemiAnalysis directly observed the consequence of SAQP in the cross-sectional images: the M0 trenches of N+3 show a pronounced inverted trapezoid profile (narrower at the bottom than the top), with a clear barrier layer enrichment zone at the trench bottom. While this morphology aids copper filling, the difficulty of process control skyrockets at this 32.5nm pitch.
To use a trader-friendly analogy: SMIC is printing banknotes of the same denomination, but each note costs multiples more to print than TSMC's, with greater yield risk. The density is the same, but the economics are entirely different.
Kirin 9030: Squeezing Every Square Millimeter of Silicon Under Constraints
HiSilicon's chip design prowess is another story.
Looking at die area, the Kirin 9030 is almost the same size as its predecessor, the 9020 (around 140mm²), but packs in more: the CPU upgraded from 1 big core + 3 medium cores to 1 big + 4 medium, GPU compute units increased from 4 to 6, an extra Tiny core was added to the NPU, and caches were expanded across the board. The density improvement from N+3 allowed Huawei to cram more logic into the same die size.
On performance, STEEL Lab referenced public benchmark data, offering a clear positioning: the Kirin 9030's GPU performance (Mali-G935) roughly matches flagship levels from 2022. Its 3DMark WLE score improved 70% over the previous generation, slightly surpassing the Snapdragon 8+ Gen 1, but compared to the current flagship Snapdragon 8 Elite Gen 5, the gap is 2.4x to 2.6x.
The CPU situation is more telling. The IPC of the big core, TaiShan Prime, is roughly at the level of Arm's Cortex-X2, a 2021 design. The IPC of Apple's M1 Firestorm core, released in 2020, remains 35% higher. The latest Apple M5 P-core's IPC is 60% higher, with absolute performance being 2.7x that of the Kirin core.
The root of the gap lies not in design, but in process technology. Apple and Qualcomm use TSMC's N4, N3P, processes that have fundamental advantages in the voltage-frequency curve: more transistors can be packed into the same area, higher frequencies can be achieved at the same power. Huawei's core designs are on par with the industry's previous generation leaders, but are trapped in manufacturing processes two generations behind.
When Process Scaling Stalled, Huawei Prepares to "Fold"
The most forward-looking part of the report is Huawei's τ scaling law and LogicFolding roadmap, presented at the 2026 ISCAS conference.
Traditional semiconductor scaling advances on a two-dimensional plane: shrinking transistors and narrowing metal lines. Moore's Law has progressed for decades, essentially doing just that. The τ scaling Huawei proposes shifts the optimization target from the spatial domain to the temporal domain, focusing on reducing time costs for data movement and processing, including transistor switching delay, signal propagation delay, and compute/memory access latency.
LogicFolding is the engineering implementation of this theory. Simply put, it splits the same logic block into top and bottom layers, stacking them face-to-face and connecting them via ultra-fine-pitch hybrid bonding. The direct benefit is shortening the longest signal paths. In modern chips, a significant portion of power and delay is spent driving long interconnects and repeater buffers. By folding logic vertically, critical paths become shorter, enabling higher frequencies and lower power consumption.
Huawei outlined an aggressive roadmap: While the Kirin 9030's big core runs at 2.75GHz, lab samples have achieved 3.39GHz, with a target of reaching 5GHz by 2031. Concurrently, through 3D stacking, the equivalent density aims to reach 295 MTr/mm², comparable to TSMC's 14A level.
SemiAnalysis remains skeptical. They point out that Huawei's density calculation method differs from traditional foundries: the density for 3D stacking is calculated based on package footprint, naturally yielding higher numbers when stacking multiple active logic layers. Using the same method to calculate AMD's MI450X (N2 top die + N3P base die) would yield a theoretical density of 460.2 MTr/mm², far exceeding Huawei's 2031 target.
However, the direction itself warrants attention. For Huawei, this path essentially involves a systems design company taking on tasks traditionally handled by foundries. AMD's V-Cache implements 3D stacking for cache, and AMD MI350X moves I/O and interconnects to the base die. What Huawei aims to do is more radical—directly splitting a single logic block and distributing it vertically. This represents a challenge of another magnitude in engineering difficulty.
Export Controls Reshape the Dimensions of the Race
SemiAnalysis' concluding point is blunt: Export controls have not stopped China's chip progress, but they have altered the path and the cost of that progress.
SMIC's N+3 proves that N6-level logic density can be achieved without EUV. But this path is more expensive, more complex, and has greater yield challenges. Every step forward increases the marginal difficulty: more masks, stricter overlay control, more costly multiple patterning. Theoretically, N+4 could reach 137.8 MTr/mm² (comparable to TSMC N5), and N+5, with the introduction of backside power delivery, could even approach Intel 18A's HP library density. But each step is harder, more expensive, and has less margin for error than the last.
Meanwhile, SMIC's N+2 and N+3 processes are being transferred to Huahong, potentially benefiting design houses like Alibaba's T-Head and Cambricon. Chip manufacturing knowledge is diffusing from a single foundry to an ecosystem, further diluting the effectiveness of sanctions against individual companies.
On the design side, Huawei and Peking University are already developing domestic EDA tool prototypes for LogicFolding. This doesn't equate to replacing the complete toolchains of Synopsys and Cadence, but domestic EDA is evolving towards "architecture-process-packaging co-optimization."
An interesting detail: STEEL found in its teardown that the DRAM in the Kirin 9030 Pro comes from Samsung (K4L2E165YD, LPDDR5X-9600, 1a node), while the 16GB Pro Max version shows packages from both Samsung and ChangXin Memory (CXMT). The CXMT chip packaging date is marked as week 45 of 2025, with process density equivalent to the industry's 1z level. This indicates that Chinese memory chips have begun entering Huawei's flagship supply chain, albeit still one to two generations behind Samsung and SK Hynix in process technology.
For investors, the signal truly worth tracking is whether Huawei's 3D stacking roadmap can, at a controllable cost, bring Chinese-produced chips to a "good enough" threshold for scenarios like smartphones, AI inference, and networking equipment.
Once "good enough" is established, the strategic value of this supply chain will be repriced.
