Authors: Ray Wang, Myron Xie, Dylan Patel et al.
Compiled by: Deep Tide TechFlow
Deep Tide Introduction: ChangXin Memory Technologies (CXMT) is about to list on the STAR Market, potentially becoming the largest semiconductor IPO in Chinese history. Founded as recently as 2016, the company started by acquiring patents and talent from the bankrupt German DRAM manufacturer Qimonda. Backed by nearly a decade of capital infusion from the Hefei government, which tolerated years of losses, CXMT turned its first annual profit in 2025, and its Q1 2026 revenue alone reached $7.3 billion. This in-depth, ten-thousand-word report from SemiAnalysis dissects CXMT's technological roadmap, financials, HBM challenges, and IPO structure, making it essential reading for understanding China's position in the memory chip industry.
The SemiAnalysis team first outlined the enormous demand for memory from AI inference and agent workflows in their newsletter as early as late 2024. Since then, they have published multiple in-depth reports on memory and have been closely tracking CXMT and China's computing ecosystem. As CXMT prepares for its IPO in the coming months, a dedicated deep dive is necessary. CXMT is likely to become China's largest semiconductor IPO and a milestone for this leading domestic memory manufacturer. From here on, competition between CXMT and Samsung, SK Hynix, and Micron will only intensify.
The Silicon Valley Returnee
Zhu Yiming, founder of CXMT, graduated with a bachelor's degree in physics from Tsinghua University in 1994 and later pursued electrical engineering at Stony Brook University. After working in Silicon Valley for years, he became a project leader at MoSys (Monolithic System Technology) around 2001. In 2005, Zhu returned to China with a set of SRAM patents and $100,000 in seed funding, founding GigaDevice, which later became one of the world's leading NOR Flash suppliers. However, the global NOR Flash market is far smaller than DRAM or NAND Flash. Zhu had bigger ambitions and chose the DRAM track.
DRAM isn't a game for fabless companies. It consumes vast capital, is heavily protected by patents, and highly dependent on manufacturing capabilities. By 2016, the entire industry had been whittled down to just three survivors: Samsung, SK Hynix, and Micron. The moats built over four decades with accumulated patents and capital seemed impenetrable for new entrants. Zhu's SRAM patents and GigaDevice's NOR Flash business offered neither DRAM cell design, DRAM process technology, nor a way around the patent barriers of the giants. Therefore, when Zhu and the Hefei municipal government launched the DRAM project "Project 506" (which later became CXMT) in 2016, core technology had to be sourced externally.
The source was a dead German company.
The DRAM Foundation: Qimonda's Legacy
That dead company was Qimonda. Qimonda went bankrupt in January 2009 due to the global financial crisis and the subsequent memory price crash, but at its peak, it was Europe's leading DRAM manufacturer. As a subsidiary of Infineon, tracing its roots back to Siemens, Qimonda offered a scarce alternative: a deep DRAM patent portfolio and a memory cell architecture originating from outside the Samsung-Hynix-Micron triangle.
In June 2015, Polaris Innovations, a subsidiary of the Canadian patent licensing company WiLAN, purchased approximately 7,000 Qimonda patents and applications from Infineon for around €30 million. In December 2019, Polaris signed an agreement with CXMT, licensing a large batch of DRAM patents. CXMT executives have publicly stated they obtained about 2.8TB of Qimonda technical documentation, which became the foundation of CXMT's DRAM business.
A key technology CXMT inherited and developed from Qimonda is the 46nm-class Buried Wordline (BWL) memory cell, advancing it towards the 10nm-class. BWL is a core architectural innovation. Traditional designs route the access transistor's gate along the wafer surface, while BWL buries the gate in a trench below the bitline. This offers three benefits: shrinking the memory cell to a 6F² layout (traditional is 8F²), extending the channel length without occupying surface area to suppress short-channel leakage (affecting data retention), and reducing gate-bitline parasitic capacitance. Buried Wordline plus stacked capacitor—this is the architecture all three major memory giants use today. Qimonda, which stuck with the trench capacitor approach, happened to retain the technology for the stacked/BWL architecture—exactly what CXMT acquired.
Talent: From Frozen Blueprints to Living R&D Capability
Beyond patents, the more enduring asset CXMT gained from Qimonda's collapse was its engineers. Qimonda had a major R&D center in Xi'an with 400-500 engineers, one of its largest outside Germany. After Qimonda's bankruptcy, while the entire Xi'an R&D center was acquired by Tsinghua Unigroup, the wider dispersion of talent benefited CXMT.
CXMT also successfully attracted senior engineer Karl-Heinz Kuesters from Qimonda's German headquarters. Kuesters had served as Vice President of Technology and Pre-development at Siemens, Infineon, and Qimonda for 24 years. The pre-development line he led was precisely the stacked capacitor approach—the architecture CXMT actually adopted. He joined CXMT as a technical advisor. EE Times referred to Kuesters as CXMT's "ace card." What Kuesters brought was tacit knowledge not captured in patents or 2.8TB of documents: two decades of experience leading DRAM development, enabling him to tell CXMT's engineers which Qimonda designs to keep, which to discard, and how to move a working memory cell from the lab into mass production. This integration and yield judgment does not exist in any patent literature.
The pattern was similar on the US side. Ping Er-xuan (the public articulator of the "46nm to 10nm-class" roadmap), CXMT's Vice President of Future Technology Assessment, did not come from Qimonda but from a US career at Micron, SanDisk, and Applied Materials, with deep experience in memory and materials technology.
CXMT also recruited extensively from South Korea and Taiwan. South Korean prosecutors have indicted former Samsung employees for leaking technology; reportedly, dozens of Korean engineers have worked at CXMT. The situation is similar in Taiwan, where CXMT consistently poaches top equipment and process engineers with generous salaries.
This is key to understanding CXMT's trajectory. Qimonda's patents are a finite, expiring asset. What enabled CXMT to progress from G4 to G5 to HBM is the assembled talent capability—locally trained talent, Chinese engineers who worked at foreign firms and returned, and a small number of foreign experts—not the documents. The legacy was just the start; talent turned an external legacy into an engine for independent R&D. But this engine burned capital for nearly a decade before turning a profit. The question is, who had the patience to keep funding it?
The Patience of State-Owned Venture Capital
CXMT's success is hard to attribute to anything other than strong support from both local and central Chinese governments. The Hefei municipal government is a classic case. Hefei has become a hub for technological innovation in China, incubating a string of successful companies over the past two decades through its "patient state-owned venture capital" model: BOE (a global leader in display panels), NIO (a leading EV manufacturer), and now CXMT.
The Hefei municipal government did two key things for CXMT.
First, it helped CXMT build a local supply chain around its fab. Hefei's playbook is: take a significant stake in the core "anchor" enterprise, then attract the rest of the industrial chain. This was done for BOE in display panels, for NIO in EVs, and replicated for CXMT starting in 2016. Around CXMT's fab in Hefei's Airport Economic Zone, the government fostered a dense local industrial cluster. Packaging and testing houses like Peidun and Xinfeng are located right next to CXMT's factory walls, with over 99% of Xinfeng's revenue coming from CXMT. Guanggang Gas operates an on-site bulk gas plant supplying most of CXMT's needs. Zhixin Semiconductor, a subsidiary of TYTech, provides wafer reclamation capacity in Hefei's Xinzhan High-Tech Zone. State-owned venture capital also directly controls upstream chip molding equipment supplier Wenyi Technology.
Second, Hefei's state-owned capital was willing to tolerate losses for a very long time. Unlike private equity funds needing to deliver returns to LPs on schedule, Hefei's state-owned venture capital is ultimately backed by municipal and development zone state-owned entities with no exit clock. They kept funding a company that didn't achieve its first annual profit until 2025, with cumulative losses of approximately 36.65 billion RMB over nearly a decade. For the first phase of "Project 506" launched in 2016, about 80% of the funding (14.4 billion RMB / 18 billion RMB) came from Hefei's state-owned capital. In subsequent funding rounds, although Hefei's stake was diluted, it never reduced its holdings or exited. By the IPO, the largest shareholder, Hefei Qing Hui Ji Dian, holds 21.67%, with state-owned venture capital collectively holding over 30%. The willingness to treat a fab as a ten-year bet rather than a fund-cycle return—this was the catalyst on which both technology and talent depended.
From Legacy to Independence
Putting the three threads together, CXMT's first decade comes into focus. Qimonda provided the foundation: a licensed patent portfolio and memory cell architecture from outside the giants' triangle. Talent provided the engine: key figures like Kuesters and Ping, returnees from US giants, and controversially recruited talent from South Korea, who turned frozen blueprints into a process that could be pushed forward. Then, the Hefei government provided what the first two needed but couldn't generate on their own: capital, patience, and a localized supply chain. All three were indispensable.
Next, we discuss CXMT's financials, technology, and equipment ecosystem.
The Next Step After a Decade: IPO in a Supercycle
CXMT's impressive story over the past decade might only be the early chapter of a longer narrative. The company is preparing for one of China's largest semiconductor IPOs in recent years, potentially one of the most-watched global semiconductor listings this year. In December 2025, the Shanghai Stock Exchange formally accepted CXMT's listing application for the STAR Market. Market rumors had been circulating throughout 2024 and 2025 about the company's IPO preparations. The latest development is that CXMT submitted its registration application to the China Securities Regulatory Commission (CSRC) on May 27 and is now in the final review stage.
CXMT's IPO prospectus discloses a wealth of previously unavailable information. Combined with SemiAnalysis's Memory Model, it allows for more precise judgment of CXMT's current position and future trajectory.
At a high level, by almost every metric, CXMT is the world's fourth-largest DRAM manufacturer and is widening its lead over secondary memory players. For full-year 2025, CXMT's revenue grew 156% year-over-year to approximately $8.6 billion (2024: ~$3.3 billion, 2023: ~$1.2 billion). Net profit also turned positive for the first time, reaching $1 billion. Even so, CXMT's 2025 revenue remains far below the DRAM revenues of Samsung (~$72.3B), SK Hynix (~$52.1B), and Micron (~$37.2B).
Caption: Global DRAM Vendor Revenue Comparison (Source: SemiAnalysis Memory Model)
In Q1 2026, CXMT reported revenue of $7.3 billion, up approximately 700% year-over-year. Quarterly revenue alone is now close to its full-year 2025 level. Operating margin also expanded sharply to around 70%.
SemiAnalysis believes this is just the beginning. Based solely on disclosures in the prospectus, the company expects H1 2026 revenue to grow over 7-fold year-over-year, exceeding $16 billion. For full-year 2026, SemiAnalysis estimates CXMT's revenue could surpass $50 billion. If achieved, this would mean the company has more than doubled revenue annually since 2023, with 2026 growth exceeding 6-fold.
The driver of this explosive growth is less about technology or market share and more about the cycle itself. Look closely at the data: In Q1 2026, CXMT's bit shipments grew only 11%, but ASP (Average Selling Price) increased by about 57%. In the prior Q3 and Q4 2025, ASP grew sequentially by 63% and 68% respectively. What truly boosted performance was explosive price increases, not a significant market share grab from peers. In terms of bit shipments, the SemiAnalysis model shows CXMT's market share will increase from 9% in 2025 to 12% in 2027. A 3-percentage-point share gain might seem modest, but in a market SemiAnalysis forecasts will approach $1 trillion in 2027, it is massive.
Caption: CXMT ASP vs. Bit Shipment Trend (Source: SemiAnalysis Memory Model)
The Flaw in the "Chinese Memory Flooding the Market" Narrative
For readers not deeply tracking CXMT or the memory market, a more interesting finding is the comparison of CXMT's pricing versus industry leaders. Data from the Memory Model challenges a common misconception: that Chinese memory is structurally cheaper and will flood the market, depressing global prices. This might have been true in some past cycles but is not accurate in the current one.
Take Q1 2026: CXMT's DRAM ASP was only about 5-10% lower than that of Samsung, SK Hynix, and Micron. SemiAnalysis expects this direction to hold for full-year 2026, but the gap will gradually widen. The widening is not due to intrinsic pricing differences but changes in product mix. Top vendors have a higher proportion of server DRAM and HBM shipments, and server DRAM pricing prospects are stronger than consumer DRAM.
By late 2027, SemiAnalysis expects server DRAM and HBM to account for over 50% of DRAM end-market demand. Since server DRAM and HBM command a higher $/GB, top vendors will further widen the ASP gap with CXMT, especially considering HBM prices are expected to rise significantly in 2027.
Caption: DRAM Vendor ASP Comparison (Source: SemiAnalysis Memory Model)
Margins: The Cycle's Gift
Strong ASP tailwinds significantly improved CXMT's margins. Full-year 2025 gross margin reached 37.8%, close to Samsung's 39.4% and Micron's 39.8%, but far below SK Hynix's 60.4% (SK Hynix benefits from a higher HBM shipment mix). CXMT's ~38% gross margin is a massive leap from -113% in 2023 and -4.7% in 2024. 2025 marked not only CXMT's highest-ever gross margin but also its first year of positive gross profit.
Caption: DRAM Vendor Gross Margin Comparison (Source: SemiAnalysis Memory Model, Company Reports)
Entering 2026, margins improved further. Q1 operating margin reached 70%, compared to SK Hynix's 73%, Samsung's 81%, and Micron's 84% in the same period. Beyond ASP growth, CXMT's margin improvement also benefited from its product mix, which is almost entirely focused on commodity DRAM—in the current environment, commodity DRAM margins are actually higher than HBM. According to the prospectus, approximately 99% of the company's bit shipments in 2025 were traditional LPDDR and DDR products, with HBM contributing minimally to revenue and profit.
Caption: DRAM Vendor Operating Margin Comparison (Source: SemiAnalysis Memory Model, Company Reports)
A simple DDR5 per-bit cost analysis makes the picture clearer. SemiAnalysis found that CXMT's DDR5 per-bit cost remains over 30% higher than the big three. But because DDR5 pricing was already very strong in Q1 2026, CXMT's gross margin was still pushed above 70%. This means CXMT's margin improvement is primarily driven by pricing, not a substantive enhancement in product competitiveness or cost structure.
Caption: DDR5 Per-bit Cost Comparison (Source: SemiAnalysis Memory Model)
Capacity Expansion: Catching Up to Micron
Beyond record profits, CXMT is also catching up in capacity. By the end of 2026, SemiAnalysis expects CXMT to reach approximately 350k wafers/month capacity, only slightly below Micron's ~385k wafers/month. Ranked by wafer capacity, CXMT could become the industry's third-largest memory manufacturer.
Caption: Global DRAM Vendor Monthly Wafer Capacity Comparison (Source: SemiAnalysis Memory Model)
But significant gaps remain with the two giants: Samsung ~720k wafers/month, SK Hynix ~595k wafers/month. By 2027, with the initial ramp of Shanghai Phase 1 and full production in Hefei and Beijing, CXMT's capacity could reach ~420k wafers/month, accounting for about 17% of global DRAM capacity, up from ~13% in 2025. In terms of bit shipments, share rises from 9% in 2025 to 12% in 2027.
By 2028, with Hefei at full production and continued ramps of Shanghai's two phases, SemiAnalysis expects CXMT to reach 500k wafers/month, representing about 17% of global DRAM supply.
Caption: CXMT Hefei Site Capacity (Source: SemiAnalysis Memory Model)
Oversupply Concerns: Not for at Least Two Years
Given CXMT's increasingly significant role in global DRAM capacity, as in every past cycle, investors worry Chinese players could create supply-demand imbalance. SemiAnalysis believes this concern is overblown for at least the next two years. Even after accounting for incremental capacity and bit shipments from CXMT and other memory players, assuming utilization rates above 90%, DRAM supply remains extremely tight.
Caption: DRAM Supply-Demand Balance (Source: SemiAnalysis Memory Model)
Looking solely at CXMT's capacity expansion pace: ~85k, 70k, and 80k wafers/month added annually from 2026-2028, compared to Samsung's 15k/50k/110k, SK Hynix's 60k/60k/90k, and Micron's 30k/90k/115k. Even with these additions, DRAM will still be in shortage by high single-digit percentages in 2026, with the deficit widening to low-to-mid double-digit percentages in 2027. SemiAnalysis has previously detailed why DRAM could remain undersupplied until 2028.
CXMT lacks the ability to irrationally accelerate capacity expansion beyond its current pace to disrupt the market, given the long fab construction cycles. The current extremely favorable pricing environment is precisely the main driver of CXMT's performance explosion—CXMT certainly wants this to continue. Tracked fab construction timelines by SemiAnalysis also show no signs of such a possibility. However, it should be emphasized that the total wafer capacity of the Shanghai site at full production could exceed 400k wafers/month.
HBM: CXMT's Dilemma
Regarding HBM, CXMT allocates a very limited portion of its wafers. As of end-2025, out of its ~265k wafers/month capacity, only about 5k were allocated to HBM. SemiAnalysis expects this to increase to ~30k by end-2026 and ~55k by end-2027. This aligns with the prospectus disclosure that ~99% of 2025 revenue came from DDR and LPDDR.
Caption: CXMT HBM Wafer Capacity Allocation (Source: SemiAnalysis Memory Model)
But this allocation pattern may change. China's push for AI computing self-sufficiency may conflict with the company's commercial priorities, and this pressure is expected to intensify over time. SemiAnalysis factors government guidance to tilt capacity towards HBM into its forecast, expecting accelerated HBM capacity expansion in 2027 and 2028. CXMT's HBM capacity is projected to reach 55k wafers/month in 2027 and 100k wafers/month in 2028, increasing its share of global HBM wafer supply from 1% in 2025 to 12% in 2028.
It's crucial to remember that CXMT, unlike other memory players, is not just an economically and technologically important company; it is a strategic asset the state can leverage to advance policy goals.
From a short-term commercial logic perspective, it makes sense for CXMT to prioritize commodity DRAM over HBM. Commodity DRAM currently has significantly higher margins than CXMT's HBM products, and bit output per wafer area is over 3x higher for commodity DRAM. In the early stages of HBM technology maturity, heavily investing in HBM capacity would consume scarce wafer starts that could be used for higher-margin, higher-volume commodity DRAM. But China must advance its HBM capabilities because HBM sales to China are strictly restricted by US export controls, with Korean vendors' shipments to China only sustained through some loopholes.
The HBM Technology Gap
Regarding technical readiness, SemiAnalysis believes CXMT is still struggling with production stability for HBM3 8-hi, with even greater challenges for 12-hi.
On the front-end, CXMT has made progress with production stability of its **G4 node (equivalent to 1z node)**, and most DRAM output in 2026 will be based on G4. However, the DRAM core die for HBM, due to larger die sizes and stricter performance requirements, should have significantly lower wafer-sort yield compared to commodity DRAM. SemiAnalysis believes front-end yield remains a major challenge for CXMT, with the gap to peers still substantial. While G4 yield has improved, the low margins in 2024 and 2025 suggest it may still be below the mature industry standard of 85-90% for the 1z node. This implies equipment limitations and manufacturing experience remain persistent hurdles.
Caption: CXMT DRAM Process Node Roadmap and Yield (Source: SemiAnalysis Memory Model)
The next-generation G5 node (equivalent to 1a), theoretically could continue without EUV lithography like Micron's 1a, but will face increasing manufacturing and design challenges. These challenges are further exacerbated when applying this node to DRAM dies for HBM.
Die stacking is the biggest obstacle for CXMT's HBM. HBM stacking typically introduces severe technical difficulties: thermal stress, die cracking, warpage, bonding defects, and yield loss from multi-layer stacking. These problems are worse when moving from HBM3 8-hi to HBM3 12-hi and HBM3E, as CXMT's manufacturing experience with 12-hi and above HBM remains limited.
The stacking challenge is not unique to CXMT. Top vendors also face issues like die cracking, thermal management, and yield loss with 12-hi HBM4. 16-hi or even 20-hi is even more problematic—one reason Rubin Ultra is expected to use 12-hi HBM4E instead of 16-hi is supply: 16-hi requires more DRAM wafers, is harder to manufacture, has higher wafer loss, and offers less effective bit supply.
SemiAnalysis believes it's increasingly likely CXMT will skip HBM3 and directly focus on HBM3E 8-hi and 12-hi. Reasons: first, customers in the 2027 timeframe will demand more competitive HBM products; second, mainstream accelerators by then will feature HBM3E, HBM4, and HBM4E.
Caption: Global HBM Roadmap Comparison (Source: SemiAnalysis Memory Model)
Regarding back-end packaging, while there's debate over whether CXMT uses MR-MUF or TC-NCF, packaging challenges are relatively more manageable, as the company and its packaging partners face fewer restrictions under export controls. CXMT has been closely cooperating with leading OSATs like Tongfu Microelectronics, and back-end capabilities should be gradually improving, though a gap with top memory vendors remains.
Based on existing manufacturing challenges, SemiAnalysis models CXMT's front-end and back-end yields for HBM3 8-hi at ~35% and ~70% respectively, for a combined yield of only about 25%. For HBM3 12-hi or HBM3E 12-hi, with higher stacking and bonding difficulty, combined yields should be even lower. At such yield levels, CXMT's HBM output per wafer start is far lower than top vendors. More critically, the HBM produced would have extremely low margins, especially compared to commodity DRAM in the current pricing environment.
CXMT's HBM dilemma is also reflected in product penetration. SemiAnalysis believes only Huawei, Cambricon, and a few emerging Chinese AI chip startups are likely to adopt CXMT's HBM, though adoption rates could be high. Domestic AI accelerator vendors still prefer to use foreign HBM3 or even HBM3E when possible, whether through available channels or pre-December 2024 export control inventories. As domestic cloud vendors' capital expenditure and computing infrastructure grow rapidly, domestic demand for HBM is also growing quickly.
One notable exception: Huawei and CXMT will develop custom HBM not based on JEDEC standards and PHY, which will help compensate for bandwidth disadvantages.
China's HBM supply constraints might be more severe than what sluggish domestic HBM development suggests. The three major HBM suppliers themselves have tight supply, and under the December 2024 US export controls, they are restricted from selling HBM2E and more advanced HBM to China. In a tight supply environment, their willingness to risk violating rules to sell to China is lower.
But HBM transshipment and smuggling complicate the picture. SemiAnalysis understands some Chinese companies are still acquiring HBM3 through various channels. Transshipment via overseas offices or third-country partners remains a path; some third-country OSATs or intermediaries facilitate these flows. Some entities export in not-fully-assembled systems or modules (not considered finished GPUs or ASICs, thus still allowed for export to China), after which the HBM is disassembled and repackaged onto domestic GPUs or ASICs.
What the IPO Structure Reveals
CXMT may become one of China's largest semiconductor IPOs, and its ownership structure is more revealing than the headline financials. CXMT reported 2025 consolidated net profit of 7.14 billion RMB, but net profit attributable to shareholders of the parent company was only 1.87 billion RMB, with 74% attributable to non-controlling interests.
The reason lies in the equity structure. CXMT holds only 30.68% of the economic rights in Changxin Xinqiao and 31.72% in Changxin Jidian Beijing, but controls 73.01% and 75.32% of voting rights respectively through long-term concerted action arrangements. This allows the company to consolidate fabs it doesn't actually own a majority of economically, thus overstating the profit actually available to public shareholders by about four times.
Caption: CXMT Consolidated Profit vs. Profit Attributable to Parent (Source: SemiAnalysis Memory Model, Company Reports)
The same voting structure also makes the company's declaration of having "no controlling shareholder, no actual controller" somewhat unconvincing (the prospectus lists this as a formal governance risk). CXMT exercises majority voting control over the fabs via the concerted action agreements, while state-owned entities like the National Integrated Circuit Industry Investment Fund Phase II and those from Hefei and Anhui will collectively hold well over 30% post-IPO. This arrangement seems designed to manage export control perceptions and foreign investor sentiment, at a time when CXMT's relationship with the Chinese government is under maximum scrutiny.
Caption: CXMT Ownership Structure Chart (Source: SemiAnalysis Memory Model, Company Reports)
Valuation: An Underestimated Floor
CXMT plans to raise 29.5 billion RMB (~$4.1B), representing 10-15% of total shares post-listing. Full financing via IPO implies: ~4.41 RMB/share at 10% dilution, ~2.78 RMB/share at 15% dilution (the June 2025 funding round price was 2.63 RMB). The lower end price shows almost no premium over the previous round, despite Q1 2026 achieving $7.3B revenue and $4.8B net profit. 2.78 RMB corresponds to a valuation of ~197 billion RMB (~$27B), only 1.8x the annualized H1 2026 profit attributable to the parent. SemiAnalysis believes this valuation floor is too low; actual pricing should be much higher.
Caption: CXMT IPO Valuation Analysis (Source: SemiAnalysis Memory Model, Company Reports)
Use of Proceeds: Focus on Commodity DRAM, No Mention of HBM
The use of the 29.5 billion RMB proceeds reinforces CXMT's current priorities. 20.5 billion RMB (69.5%) is for wafer production lines and DRAM technology upgrades, and 9 billion RMB (30.5%) for forward-looking DRAM R&D. The prospectus discloses no dedicated HBM projects, not even mentioning HBM. Project descriptions focus on newer process platforms, product iterations, and migrating existing lines to mid-to-high-end DRAM. The core role of the IPO is to strengthen CXMT's DRAM manufacturing and technology foundation, with no public funding commitment for near-term HBM expansion.
Caption: CXMT IPO Proceeds Allocation (Source: SemiAnalysis Memory Model, Company Reports)
A Cycle-Timing Warning
The magnitude of profit swings requires a reminder about cycle timing. In its December 2025 prospectus, CXMT expected a full-year 2025 loss attributable to the parent of 0.6-1.6 billion RMB. Five months later, the updated prospectus reported a profit of 1.87 billion RMB, with consolidated profit over twice the high-end estimate. This also shows how quickly top-of-cycle pricing can change the valuation denominator—in both directions.
Alibaba's Dual Role
A final detail: Alibaba's role on CXMT's shareholder list changes how to interpret CXMT's demand side. Alibaba Cloud is both a core hyperscale customer and a shareholder with close to 4% ownership and endorsement, alongside Zhu Yiming's GigaDevice (~1.8%). To some degree, the scale of domestic demand is secured, an advantage Korean giants don't have in their home market. The percentage is small, but the significance is far greater.
Note: The latter part of this article, covering in-depth analysis of CXMT's equipment ecosystem, export control impacts, and China's memory and computing ambitions, is paid content from SemiAnalysis and is not included in this compilation.
