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The "Iron Rule" of Chip Equipment Is Being Broken

For years, the semiconductor equipment industry followed an unwritten "iron rule": suppliers offered steep discounts for new tool introductions (Design-in) and faced consistent price pressure during repeat orders, especially during market downturns. This long-standing buyer's market dynamic is now being upended. Recently, SK Hynix's primary equipment suppliers have reportedly requested a 3-4% price *increase*, a nearly unprecedented move. This shift is driven by a severe supply-demand imbalance fueled by the AI compute boom. Securing equipment has become an urgent arms race as chipmakers' expansion speed dictates their ability to fulfill massive AI chip orders. Key areas feeling the strain include: **TCB (Thermal Compression Bonding) Equipment:** Demand is exploding, driven by the simultaneous needs of HBM4 memory stacking, AI chip Chip-on-Substrate (C2S), and logic Chiplet Chip-on-Wafer (C2W) packaging. Players like Hanmi Semiconductor, Hanwha Semitech, and ASMPT are receiving major orders. While hybrid bonding is seen as the future, TCB remains the pragmatic choice for HBM4 mass production, with its lifecycle extended by relaxed specifications and ongoing technological upgrades. **Test Equipment Bottlenecks:** Ironically, AI-driven shortages are now crippling test equipment manufacturing. Critical components like FPGAs, Driver ICs, and CPUs face severe shortages and extended lead times (up to 52 weeks for FPGAs), as AI data center and server vendors prioritize supply. This creates a paradoxical cycle: AI chip shortages drive fab expansion, which requires more test equipment, whose production is delayed because its key parts are diverted to make AI chips. The industry is entering a broad, AI-powered upcycle. SEMI forecasts global semiconductor equipment sales to hit a record $156 billion by 2027, fueled by investment in advanced logic/foundry, HBM-driven DRAM, and advanced packaging (like CoWoS). Major players like TSMC, SK Hynix, and Micron are aggressively ramping capital expenditure. In conclusion, leading equipment vendors are no longer just selling tools; they are selling the critical capability to deliver AI-era capacity. Pricing power is shifting decisively to those with indispensable technology in key process nodes like advanced logic, HBM, and advanced packaging, rewriting the industry's traditional power structure.

marsbit06/21 01:57

The "Iron Rule" of Chip Equipment Is Being Broken

marsbit06/21 01:57

The Tao (τ) Law Makes EDA Go Viral

In May 2026, Huawei's semiconductor division introduced the "Tao (τ) Law" at IEEE ISCAS, shifting the industry focus from Moore's Law's geometric scaling to "time scaling." Unlike traditional approaches relying on transistor miniaturization, τ Law optimizes the time constant (τ) across device, circuit, chip, and system levels to improve information processing speed and efficiency. Huawei has already applied this principle, mass-producing 381 chips across various applications, with a target to achieve performance equivalent to 1.4nm technology by 2031. The implementation of τ Law, involving techniques like Chiplet, 3DIC, and Logic Folding, places new demands on EDA tools, highlighting gaps in current offerings. Traditional 2D or pseudo-3D EDA flows lack native support for true 3D design, cross-layer co-optimization (STCO), and coupled multi-physics analysis (thermal, power, stress), which are crucial for advanced integration. Chinese EDA companies, such as Empyrean Software, Primarius Technologies, and Xpeedic, are evolving from point-tool specialists to providing full-flow, system-level solutions. For instance, Peking University has developed a prototype "true 3D" EDA tool showing significant improvements in wirelength and timing. Empyrean Software has also launched a comprehensive 3DIC design and verification platform. The τ Law framework presents an opportunity for the domestic EDA industry to transition from achieving basic functionality to developing robust, integrated toolsets essential for next-generation chip design.

marsbit06/12 13:39

marsbit06/12 13:39

After Marvell's 32% Surge, the Chinese Chip Family Behind It Emerges

The stock price of Marvell Technology surged 32.5% on June 2nd, driven by NVIDIA CEO Jensen Huang highlighting its custom ASICs and optical interconnects as core to AI data center architecture. This event brought attention to the Chinese semiconductor family behind Marvell: the Dai siblings. The story centers on three siblings, all UC Berkeley graduates, whose three-decade entrepreneurial journey aligns with major semiconductor industry shifts. In 1995, youngest sister Dai Wei Li co-founded Marvell with her husband Sehat Sutardja and his brother, focusing on storage controllers. Eldest brother Dai Wei Min founded EDA company Ultima, later sold to Cadence, and later founded VeriSilicon (芯原) in China, becoming a leading semiconductor IP provider. Second brother Dai Wei Jin co-founded EDA firm Silicon Perspective (sold to Cadence) and GPU IP company Vivante, later acquired by VeriSilicon. The combined "Dai-Sutardja" family network extends beyond Marvell. Their ventures and investments form a comprehensive ecosystem for the post-Moore's Law, chiplet era. Key holdings include: Dream Big Semiconductor (AI SuperNICs, acquired by Arm), Alphawave (high-speed SerDes IP, acquired by Qualcomm), and Silicon Box (a chiplet advanced packaging foundry). VeriSilicon itself thrives on the AI ASIC and IP boom in China. Collectively, the family's AI infrastructure-related portfolio is estimated at over $22 billion. Their strategy represents a distinct path: building critical components for open standards and key manufacturing capacity in the chiplet era, rather than pursuing standalone AI chip dominance. While this path may not create the next NVIDIA, it has enabled repeated successful exits and sustained influence within the global semiconductor industry.

marsbit06/03 11:16

After Marvell's 32% Surge, the Chinese Chip Family Behind It Emerges

marsbit06/03 11:16

Huawei's "Tao Law": A Comprehensive Overview of Core Companies

Huawei's "Tau Law": Core Companies Overview On May 25, 2026, Huawei's Director and President of the Semiconductor Business Division, He Tingbo, formally introduced the "Tau (τ) Law" at ISCAS 2026, marking a significant principle guiding industry development in the global semiconductor field from China. The Tau Law shifts focus from traditional Moore's Law, which pursues geometric transistor scaling, to "time scaling"—continuously compressing signal propagation delay (time constant τ) without solely relying on extreme feature size reduction. The core implementation path is "logic folding." This technique transforms circuit layouts from two-dimensional planes to multi-layer 3D stacks, using short vertical interconnects to replace long horizontal wiring, thereby drastically reducing τ. Huawei has already designed and mass-produced 381 chips following this principle over the past six years, with plans to launch a Kirin chip utilizing logic folding in Fall 2026. By 2031, high-end chips based on the Tau Law are expected to achieve performance levels equivalent to a 1.4nm process node. This development impacts several key industry segments, with related Chinese companies poised to benefit: 1. **EDA Design Software**: Essential for circuit-level optimization. Key players include: * **Empyrean Technology** (Huada Jiutian): China's largest full-flow EDA provider. * **Primarius Technologies** (Gailun Dianzi): Specializes in device modeling and verification. * **Semitronix** (Guangliwei): Focuses on yield enhancement and test chip EDA. 2. **Chiplet & Advanced Packaging**: Logic folding's 3D stacking necessitates advanced packaging (e.g., TSV, hybrid bonding). Core participants are: * **Tongfu Microelectronics**: A leader in advanced packaging and a key partner for AMD's Chiplet products. * **JCET Group** (Changdian Keji) & **Tianshui Huatian Technology**: Major OSATs with advanced packaging capabilities. * **VeriSilicon** (Xinyuan Gufen): Provides Chiplet-based design platforms and IP. 3. **Foundry Manufacturing**: Optimization must be implemented in transistor structures and process parameters. Potential foundries for Huawei's future chips include: * **SMIC**: China's leading foundry with advanced FinFET capabilities, the most likely candidate for next-gen Kirin chips. * **Hua Hong Semiconductor** (Huahong Gongsi): A leader in specialty processes (power, embedded memory). * **Nexchip Semiconductor** (Jinghe Jicheng): Major foundry for display driver ICs and MCUs. The Tau Law represents a strategic move towards architectural innovation and design-process co-optimization, driving demand across the domestic semiconductor supply chain.

marsbit05/25 11:33

Huawei's "Tao Law": A Comprehensive Overview of Core Companies