On May 25, 2026, at IEEE ISCAS 2026, He Tingbo, President of Huawei's Semiconductor Business Unit, introduced a key concept: The Tao (τ) Law. τ, the time constant in circuit theory, determines the speed at which a signal switches from one state to another. This marks the first time a Chinese enterprise has proposed a new principle guiding industrial development in the global semiconductor field.
More concretely, over the past six years, Huawei has mass-produced 381 chip models based on this law, covering core scenarios such as wireless base stations, AI inference, and network processors. This is not a blueprint; it's a proven path. It is projected that by 2031, high-end chips based on the τ law will achieve performance equivalent to a 1.4nm process node, maintaining long-term competitive parity with international mainstream technology roadmaps.
Today, this Greek letter is quietly reshaping the value structure of the semiconductor industry and bringing EDA from the backstage to the forefront.
To understand what impact τ will have on the EDA industry, one must first grasp what the τ law actually entails.
"Time Miniaturization" Has Just Taken the Stage: What's the Basis for the τ Law?
Moore's Law, proposed by Intel co-founder Gordon Moore in 1965, states that the number of transistors on an integrated circuit doubles approximately every 18 to 24 months, while performance increases and cost decreases.
For over half a century, this logic has functioned effectively, underpinning PCs, the internet, smartphones, and today's artificial intelligence. The industry chain also formed a tacit rhythm around it—lithography machines, materials, design, all sectors advanced collaboratively on the path of miniaturization. However, around 2000, dozens of foundries could follow the most advanced process nodes. By 2025, that number had plummeted to just three: TSMC, Samsung, and Intel, with the price for a single TSMC 2nm wafer even exceeding $30,000.
It can be said that the dividends of Moore's Law are gradually diminishing. The industry has now explored multiple technical paths, including "Huang's Law" proposed by NVIDIA CEO Jensen Huang, "More than Moore" proposed by the International Technology Roadmap for Semiconductors (ITRS), and the Chiplet and advanced packaging technologies primarily promoted by AMD and TSMC. Among these, Huang's Law emphasizes doubling the AI inference performance of a single GPU chip annually but still relies on process iteration and core stacking, essentially continuing the geometric scaling approach. "More than Moore" adds value through the integration of analog/RF/sensor functionalities but cannot directly solve the digital logic delay wall problem. Chiplet, while using "building blocks" to alleviate yield and cost issues, introduces significant inter-die interconnect delays, which may become a bottleneck in scenarios highly sensitive to latency.
Most of these solutions still adhere to the logic of "geometric miniaturization" or functional stacking, which differs fundamentally from the τ law.
The core of the τ law is "time miniaturization" replacing "geometric miniaturization," constituting a complete optimization system spanning four levels: device, circuit, chip, and system. It is suitable for large-scale system-level performance enhancement and holds particular advantages in AI and heterogeneous computing scenarios.
He Tingbo elaborated on this in detail: At the device level, by optimizing transistor and interconnect resistance along with parasitic capacitance, the device-level time constant τ is minimized from the physical foundation to the greatest extent. At the circuit level, logical folding technology breaks through the physical boundaries of traditional planar layouts, significantly shortening the wire length of critical paths and effectively reducing signal propagation resistance and capacitive loads, achieving substantial improvements in transistor density and circuit performance. At the chip level, through full-stack software-architecture-chip co-design, fine-grained control of instruction and data flow based on actual workloads enhances system-level parallelism and efficiency, significantly reducing end-to-end execution time. At the system level, defining the Lingqu Bus reconstructs computing system interconnect protocols, enabling unified memory addressing and native memory semantics across super-nodes, greatly reducing system communication latency.
In comparison, the τ law aligns more closely with the core essence of chip computing power: the primary function of a chip is information processing, and end-users are also more concerned with the latency performance of information processing rather than transistor count or process dimensions. This law provides a completely new technical roadmap for chip design that departs from reliance on pure process scaling, meaning it holds the potential to create chips with satisfactory comprehensive performance even without using the most advanced lithography equipment. Therefore, it is not contradictory to Moore's Law; the two are compatible. It can be understood as: Moore's Law continuously draws finer grids on a flat plane, while the τ Law folds the paper, using three-dimensional space to obtain shorter signal paths.
Notably, the implementation of each layer of the τ law relies on a key player—EDA. It is no longer a "drawing tool" in the traditional sense but has become the central nervous system translating "time miniaturization" from theory into physical chips.
A Huawei paper indicates that on the technical route, a co-existing and superimposed approach of Chiplet advanced packaging, three-dimensional integrated circuits (3DIC), and Logic Folding is adopted to achieve recombination and optimization at different granularities in vertical integration. To achieve hardware integration density improvement exceeding 100-fold by 2035, three major challenges are faced: an EDA toolchain generation gap, cross-wafer process variation, and the law of conservation of energy.
Andrew B. Kahng, Distinguished Professor of Computer Science and Engineering and Electrical and Computer Engineering at the University of California, San Diego, also noted that as the "tailwind" from the traditional "Moore's Law" gradually weakens, these fundamental objectives in EDA and physical design will become increasingly important.
Therefore, EDA has been repositioned to the center of the table.
What New Requirements Does the Tao (τ) Law Pose for EDA?
Regarding the new demands the τ law places on EDA tools and the existing shortcomings of traditional EDA tools, the author engaged in discussions with industry practitioners.
First, the lack of native true 3D design and cross-layer co-optimization capabilities highlights the importance of STCO.
Firstly, Peking University pointed out that traditional 2D design flows, and even the current mainstream "pseudo-3D" flow—where after synthesis each module is "fixed" onto a specific die at once, and then 2D EDA tools are used to implement each die sequentially—cannot achieve cell-level flexible allocation across layers.
Native 3D EDA tools integrate multiple dies into a unified three-dimensional design space, supporting free placement of standard cells across dies while enabling cross-die logic restructuring and global optimization. This provides critical support for translating the logic folding concept from design theory into physical implementation.
"Pseudo-3D" flow vs. "True-3D" flow. Source: Peking University
Additionally, there is a deficiency in cross-layer co-optimization capabilities. Xpeedic Semiconductor told Semiconductor Industry Insights: Chiplet, 3DIC, and LogicFolding are implementations at different granularities along the same vertical integration main line.
Chiplet combines heterogeneous dies in a 2.5D or 3D manner at the packaging level, moving communication originally within a monolithic SoC to between dies via interconnect standards like UCIe, trading modularity for yield and flexibility. 3DIC further introduces high-density TSVs and hybrid bonding between dies, vertically stacking logic, memory, and analog functions within the same package, compressing interconnect distances from millimeter to micrometer scales. LogicFolding goes a step further—it does not establish interconnects between dies but rather vertically splits and re-distributes "the internal logic of a single chip itself" at the active layer level, allowing the hybrid bonding interface to participate directly in the timing optimization of critical paths like an additional metal layer.
The three are not substitutes but co-exist in a superimposed manner within advanced packaging systems. This superposition brings a fundamental design engineering challenge: when a single package involves UCIe interconnects between Chiplets, inter-layer hybrid bonding in 3D, and intra-die LogicFolding critical path folding, the analysis boundaries for signal integrity, power integrity, thermal distribution, and mechanical stress can no longer be closed independently at any single level.
The proposal of STCO (System-Technology Co-Optimization) aims precisely to break down this fragmentation from a methodological perspective. It demands treating logical architecture, physical layout, multi-physics fields, packaging structure, and even workloads as a unified design space, conducting joint optimization searches across disciplines and abstraction levels. And this capability is the most fundamental gap in the current EDA toolchain.
Second, the lack of multi-physics coupling.
This is one of the most hidden yet critical weaknesses of traditional EDA tools. In the monolithic chip era, power delivery analysis, thermal simulation, and stress calculation belonged to separate, independent toolchains, each with its own modeling, solving, and signoff. But in 3D stacking, this model is no longer fully viable. After vertical integration of multiple dies, power density multiplies, heat dissipation paths become highly asymmetric, and inter-layer temperature differences increase. The resulting thermal expansion mismatch propagates through microbump and hybrid bonding interfaces within the stacked structure, both skewing device electrical characteristics and posing mechanical reliability risks.
What Capabilities Do EDA Vendors Need to Build?
Currently, domestic EDA companies mostly focus on point breakthroughs, tackling tough challenges in their respective specialized segments. From analog simulation to physical verification, from yield enhancement to layout design, a group of excellent domestic EDA enterprises have already formed usable and competitive point tools across many areas.
For example, Empyrean Technology is one of the earliest companies in China engaged in EDA R&D. Empyrean Technology, with analog EDA as its foundation, has gradually expanded into digital, advanced packaging, and other fields, striving to build a full-flow toolchain. Primarius Technologies follows an "underlying penetration" route. It doesn't directly tackle the full flow but relentlessly focuses on device modeling and circuit simulation. UniVista is a leading domestic digital EDA company, representing the full-flow/platform type. Xpeedic Technology chose to show its strength in the most challenging "signoff" stage. Xpeedic Semiconductor primarily focuses on "advanced packaging." Semitronix emphasizes yield enhancement and is the only company capable of forming a complete closed loop through "equipment data collection + software data analysis."
The τ law is expected to propel domestic EDA from "point tool localization" to an industrial software foundation characterized by "full-flow, cross-level, strong co-optimization." This means the EDA toolchain will no longer merely undertake auxiliary functions like circuit drawing, layout design, and backend verification. Instead, it will need to be comprehensively embedded in all key processes across the entire chain: device modeling, PDK construction, circuit simulation, parasitic parameter extraction, timing/power analysis, physical verification, advanced packaging, and system-level co-optimization.
On May 26, the School of Integrated Circuits at Peking University announced a key breakthrough in the prototype of a "true 3D" EDA tool developed to meet the Logic Folding demands of the Tao Law. This tool supports comprehensive three-dimensional space co-optimization, enables cross-die logic free allocation and joint thermal optimization, and can cover designs with tens of millions of instances. Compared to traditional "pseudo-3D" methods, Peking University's "true 3D" EDA achieves: an average wire length reduction of approximately 30%; WNS improvement of about 6%, TNS improvement of about 12%; and a peak temperature reduction of over 3%. The tool has currently completed industrial-level design verification, with subsequent plans to extend to multi-die stacking and heterogeneous integration scenarios, aiming to fill the key gap in 3D chip design.
On the same day, an investor asked Empyrean Technology on an interactive platform: Against the backdrop of the post-Moore era, the industry believes the importance of EDA is evolving from a traditional design tool towards a "system-level performance optimization platform." What is the company's view on the strategic value of future EDA in logic folding, timing optimization, and multi-chip co-optimization?
Empyrean Technology subsequently responded: The company foresightedly observed that current AI, GPU, memory, and other chips are leveraging 3DIC technology to break through the bottlenecks of advanced processes and computing power in the post-Moore era. It has made early-stage layouts in the 3DIC design EDA field, constructing a full-flow solution covering from heterogeneous integrated 3D chip co-design to verification, filling the gap for high-end 3DIC design tools in China, and is the only domestic provider of a full-flow 3DIC design and verification EDA solution. The company launched the first industry-leading Argus 3DIC physical verification platform, fully supporting 2.5D/3D heterogeneous integrated packaging design, enabling full-link physical verification from 3DIC diversified co-design to packaging.
Thus, a path gradually becomes clear: from the theoretical guidance of the τ law, to system architecture definition, and then to the strengthening of the domestic EDA toolchain. In the coming years, vendors who first introduce industrially validated closed-loop solutions for timing closure in logic folding, 3D multi-physics coupling signoff, and full-stack STCO co-optimization are likely to occupy a more proactive position in the "time miniaturization" trend. For domestic EDA, this may provide a window period to shift from point-tool catch-up to building full-stack capabilities—no longer merely aiming for "usable," but continuously evolving towards full-stack "excellent usability."
This article is from the WeChat public account "Semiconductor Industry Insights" (ID: ICViews), author: Feng Ning
