Significant changes are underway in Samsung Foundry's advanced node roadmap.
Samsung originally planned to mass-produce its 1.4nm process in 2027, but this timeline has now been adjusted to 2029. In other words, before moving towards 1.4nm, Samsung will continue to expand and optimize around its 2nm process, focusing its efforts over the next few years on process maturity, yield improvement, and customer adoption. Back in 2022, Samsung announced plans for 1.4nm mass production in 2027. The delay to 2029 means this goal is now two years later than initially planned, indicating Samsung will need to deepen its work on the 2nm platform for another three years from now until 2029.
Samsung's strategy in advanced nodes has historically been quite aggressive, particularly with its early adoption of GAA (Gate-All-Around) transistors at the 3nm node, aiming to establish a differentiated advantage and catch up to TSMC through faster node iteration. However, as the industry enters the 2nm era, the technical difficulty and capital investment for advanced nodes are rising rapidly. The competition is no longer just about "who enters the next node first."
For a foundry, the ultimate value of a new process node depends on yield, performance, power efficiency, customer count, and production cost. Therefore, rather than pushing for 1.4nm too early, a more pragmatic choice for Samsung at present might be to first mature the 2nm platform and then extend its commercial lifecycle through various derivative processes.
In reality, Samsung is not standing still at 2nm. In addition to the standard SF2, Samsung is also advancing derivative 2nm processes tailored for different application scenarios and plans to introduce technologies like backside power delivery in more advanced versions. For AI and HPC chips, as die sizes continue to expand and power consumption increases, the power delivery network has become a critical factor affecting performance. Thus, what Samsung truly needs to address in the coming years is not "how to make 1.4nm as soon as possible," but how to make 2nm a more mature, reliable, and scalable platform for mass production.
Why is Samsung Not Rushing to Adopt High-NA EUV?
Notably, Samsung is not in a hurry to make High-NA EUV, or high numerical aperture extreme ultraviolet lithography, a mandatory technology for the mass production of 2nm and 1.4nm nodes. Park Chang-min, Vice President of Technology at Samsung Electronics, previously stated that the company hopes to apply High-NA EUV to mass production of advanced nodes like 2nm and 1.4nm in the future, but the technology still requires further maturation. Samsung believes that High-NA EUV will likely become essential for mass production of advanced nodes starting from A10 and below, meaning the 1nm class and beyond. Samsung is currently conducting joint development with industry partners.
The primary advantage of High-NA EUV is its higher numerical aperture, which can further improve lithography resolution, thereby reducing the need for some complex multi-patterning processes and supporting the fabrication of more advanced transistors. However, the challenges are equally significant. High-NA EUV equipment is extremely expensive, and the exposure field size is smaller compared to traditional EUV, which may necessitate more stitching for increasingly larger AI and HPC chips. Additionally, supporting elements like photoresists, photomasks, pellicles, and computational lithography also need simultaneous upgrades. Therefore, for foundries, High-NA EUV is not simply a matter of "the more advanced the technology, the better." It is a long-term investment requiring a comprehensive consideration of equipment cost, chip area, yield, capacity, and PPA (Power, Performance, Area) benefits.
This is one of the key reasons why Samsung does not currently view High-NA EUV as an essential technology for 1.4nm mass production. For Samsung, if the 1.4nm process can still be achieved using the mature Low-NA EUV system, there's no need to prematurely bear the additional costs and process complexity brought by High-NA EUV just for the sake of higher lithography resolution. In contrast, waiting for High-NA EUV to mature further and reserving its value for the 1nm-class and below nodes may be a more pragmatic choice.
Advanced Nodes Enter the 'Era of Cost-Benefit Analysis'
From this perspective, Samsung's delay of 1.4nm does not signify a slowdown in advanced node competition. Instead, it indicates the industry is entering a new phase. Over the past decade-plus, the core of advanced node competition was "who enters the next node first," with the node number itself (28nm, 16/14nm, 10nm, 7nm, 5nm, 3nm) being a crucial indicator of a foundry's technical prowess. However, at 2nm and below, the cost of pursuing node scaling alone is becoming prohibitively high. Technologies like GAA, backside power delivery, EUV, and High-NA EUV require massive R&D and capital investment, while the performance and density gains per generation might not maintain their historical pace.
Simultaneously, the real challenge for advanced nodes is no longer just "making it work" but "making it work consistently." This is especially true as die sizes for AI GPUs and HPC chips keep growing. The larger the chip area, the higher the wafer fabrication yield requirements become. Even if a process can achieve higher transistor density, if its yield ramp is slow and wafer costs are too high, customers may ultimately be unwilling to adopt it. Therefore, foundries now need to calculate not just how much transistor density improves or performance increases, but also how many good chips can be produced per wafer and whether customers are willing to pay a higher price for these gains.
More importantly, the value of advanced nodes is no longer derived solely from transistor scaling. Chiplet, 3D stacking, HBM, and advanced packaging are all becoming key means to enhance AI chip performance. The final performance of an AI chip now depends on multiple factors: the compute die, HBM, interconnects, power delivery, thermal management, and packaging. Thus, the future competition in advanced nodes will essentially shift from a pure "node race" to a comprehensive contest encompassing technology, cost, and ecosystem. Samsung's extension of the 2nm lifecycle can be seen as a rebalancing of technological progress and commercial returns, but the prerequisite is that it must genuinely improve 2nm yields and customer scale within these three years.
TSMC's Lead with A16
The issue is that while Samsung slows its pace, TSMC is not waiting. TSMC's N2 has entered mass production, and its first post-2nm node, A16, is scheduled to enter mass production in the second half of 2026. This means that while Samsung is still refining its 2nm family, TSMC has already begun moving towards the 1.6nm class.
One of the most significant changes in A16 is the introduction of TSMC's SPR (Super Power Rail) backside power delivery technology. In traditional chips, power and signal lines are mainly concentrated on the front side of the transistors. As process dimensions continue to shrink, front-side routing resources become increasingly scarce, leading to greater competition between power delivery and signal networks. This results in routing congestion and IR Drop issues. Backside power delivery relocates the power paths to the back of the chip, freeing up more front-side routing resources for signal transmission while also shortening the power path and reducing power delivery impedance, thereby improving power efficiency in advanced nodes.
Data released by TSMC shows that compared to N2P, A16 can achieve an 8% to 10% speed improvement at the same power level, or a 15% to 20% power reduction at the same speed, with chip density increasing by up to about 10%. This indicates that the significance of A16 is not merely progressing the node from 2nm to 1.6nm, but also further unleashing the performance potential of advanced nodes through backside power delivery. Especially for AI and HPC chips, as chip sizes expand and power consumption keeps rising, power integrity and signal integrity have become as critical as the transistors themselves.
Indeed, backside power delivery has become a key technology direction for 2nm and below advanced nodes. Intel is introducing PowerVia in its 18A, TSMC is adopting SPR in A16, and Samsung is also advancing related technologies. It's clear that advanced node competition has expanded from the transistor structure itself to the synergy between power delivery, interconnects, design, and manufacturing processes.
It is particularly worth mentioning that TSMC previously stated it would take a cautious stance on High-NA EUV. From the perspective of Samsung's current delay, TSMC has once again made a winning bet.
In Conclusion
Samsung's 2nm roadmap over the next three years actually faces considerable pressure. On one hand, it needs to continue improving the yield and customer adoption rate of its 2nm process. On the other hand, it must contend with TSMC's A16 and the ongoing advance of subsequent, even more advanced nodes. By 2029, when Samsung finally launches 1.4nm, TSMC and Intel will likely have entered a new technological phase.
This also means that future advanced node competition will be difficult to measure simply with numbers like "2nm, 1.4nm, 1nm." Technologies such as GAA, backside power delivery, EUV, High-NA EUV, DTCO, and advanced packaging will collectively determine the final performance and cost achievable by a chip. The competition in advanced nodes is shifting from "whose node is more advanced" to "who can turn advanced technology into a scaled, commercial product at a reasonable cost."
Samsung is not abandoning 1.4nm; rather, it is using the next three years to truly mature 2nm, achieve scale, and secure customers. However, a question follows: when Samsung finally moves towards 1.4nm in 2029, where will TSMC and Intel be? That might be the most noteworthy aspect of this advanced node competition.
This article is from the WeChat public account "Semiconductor Industry Observation" (ID: icbank), authored by the Editorial Department.
