For the past 60 years, the semiconductor industry has been driven by shrinking transistor sizes (Moore's Law) for progress—making them smaller, denser, and cheaper.
But now this path is stalling:
- Benefits of processes below 7nm plummet
- Lithography machine costs are astronomical
- Design cost for a single advanced-node chip exceeds $10 billion
- Cost per transistor is no longer falling, but rising
Huawei's semiconductor team, after 6 years and verification across 381 mass-produced chips, has identified a new direction:
Stop competing on size, start competing on time.
They propose the τ Scaling theory (τ Scaling):
Treat "time" as the core optimization metric, compressing the characteristic time τ across the entire technology chain—from transistor switching (picoseconds) to data center tasks (seconds), covering 12 orders of magnitude.
Simply put:
It used to be about who is smaller; now it's about who is faster, has lower latency, and higher efficiency.
1. What Exactly is τ Scaling?
τ represents the delay/time constant at each layer, divided into four levels:
- Transistor: Switching speed
- Circuit: Signal transmission delay
- Chip: Computation and memory access latency
- System: End-to-end communication and synchronization time
The goal is to compress τ stack-wide. Process, circuits, architecture, and systems are optimized using the same set of metrics, ending siloed optimization.
2. Mobile Implementation: LogicFolding
Without advancing the process node, chips are stacked vertically. Ultra-precise hybrid bonding splits critical paths across multiple layers, essentially "adding floors" to the chip.
- Transistor density: Increased by 55% in one generation, from 155→238 million/mm²
- Energy efficiency: Improved by 41%, with main frequency rising nearly 13%
- SRAM frequency: Increased by over 40%
- Kirin 2026 target: 3.1GHz main frequency, aiming for 4GHz by 2029
3. AI Data Center Implementation: End-to-End Latency Reduction
In AI clusters, 80% of energy consumption and 70% of cost come from data movement. The core is reducing communication time.
1. Unified Bus
Removes multi-layer protocols, slashing remote access latency from tens of microseconds to about 100 nanoseconds—500 times faster.
2. Hi-ONE Optical Interconnect
Single module achieves 8Tb/s. Replaces copper with fiber optics, extending distance from 1 meter to 100 meters, suitable for 10,000-card clusters.
3. 3D Folding
Solves the problem of "area scaling outpacing I/O scaling" in 2.5D packaging. Moves memory, power delivery, and optical interfaces to vertical layers, scaling them in sync with computing power.
- Prediction: AI hardware integration density to increase over 100x by 2035
4. Logic and Memory Re-integration
CPUs and memory developed separately in the past. In the AI era, where data movement is more critical than computation, memory and logic must be tightly 3D integrated. Industry influence is shifting towards memory and packaging.
5. Remaining Challenges
- EDA tools need to adapt to 3D stacking design
- Optimization needed for wafer-to-wafer process variations and vertical interconnect loss
- New standards for energy efficiency and benchmarks required
Conclusion
The size-centric era of Moore's Law is over; the era of time scaling has begun.
Without fixating on cutting-edge lithography machines, continuous improvements in performance and energy efficiency are still achievable through 3D stacking, system architecture, and interconnect optimization.
This will be the core trajectory for semiconductors in the next decade.
