This week, a piece of not-so-small news came from NVIDIA: the next-generation Vera CPU for AI data centers could be ordered by Chinese clients as early as August, with a single chip priced far beyond $20,000. A full cabinet containing 256 such chips costs roughly $10 million. It's reported that a major Chinese cloud service company is considering ordering over three hundred dual-socket servers first, each packing two Vera CPUs, to test them in overseas data centers before deciding on a formal order.
Vera is NVIDIA's first standalone CPU specifically designed for agent AI, released this March. Based on Arm technology and in full production, it claims to run 1.8 times faster than competing processors. NVIDIA CEO Jensen Huang himself admitted that due to factors like export controls on advanced chips, the company's market share in China has actually declined significantly. In this context, placing Vera in Chinese clients' ordering systems is both a commercial move and a reshuffling of the cards on a table that has been nearly cleared. NVIDIA's fiscal year expectations for the Vera product line are $20 billion.
But reading this news from the Chinese perspective reveals another layer of meaning. Vera is still an Arm architecture CPU. Its ordering process, long-term supply stability, and price negotiation power are all held in others' hands.
As China's AI infrastructure voraciously absorbs computing power, must the CPU layer be bet on Arm's table? Beyond the mature, almost monopolistic mountains of x86 and Arm, is there another track that can resist Arm's gravitational pull while bearing the weight of high-performance computing?
During several recent visits to cities in the Yangtze River Delta, I repeatedly heard the same name mentioned: RISC-V.
It sounds like an old story; after all, RISC-V was born over a decade ago, with shipments in embedded fields long surpassing tens of billions. What's pushing it onto agendas repeatedly these past one or two years isn't the embedded market, but the signs of its ceiling being pushed higher, again and again, on the data center, server, and AI computing front.
What we are trying to answer is this seemingly old but actually new question.
Xu Tao, Chairman of StarFive Technologies, who was just appointed the first President of the Hong Kong RISC-V Alliance, judged years ago that RISC-V has the potential to divide the world with x86 and ARM, and that it's up to people to make it happen: "The best way to predict the future is to create it."
So, when NVIDIA knocks on the door with Vera, is the only viable path for China's self-developed CPUs to "follow Arm's lead"? Does another track exist, and where does it lead?
"Impossible Trinity" Awaits Breaking
Dr. Dai Weimin, founder of VeriSilicon, framed the industry's dilemma as a multiple-choice question at last year's industry summit. This question has since been adopted by the industry and gradually called the "impossible trinity" of the CPU industry.
Its three corners are prosperity, controllability, and autonomy.
The first combination is x86: prosperous but uncontrollable, with the thickest global ecosystem, the most complete software, and the strongest performance, yet it's someone else's private domain. The second combination, seeking controllability, involves spending enough to buy licenses, modify, and use, but the architecture is fundamentally defined by others, lacking true autonomy. The third combination, autonomous and controllable but inevitably less prosperous, involves various privately defined instruction sets behind closed doors—technically viable but destined to swim in small ponds ecologically. These three combinations correspond to the current realities of x86, the Arm licensing route, and some domestic CPUs today.
These three corners—you can only ever achieve two of them. That is the core of the impossible trinity.
Dr. Dai Weimin positions RISC-V outside this triangle. He believes that currently, the only path with the potential to be both autonomous, controllable, and genuinely prosperous is RISC-V.
The reason isn't that it has already won today, but that its structure inherently possesses the possibility of "having all three": The open-source and open instruction set means no single company can choke the industrial chain at a single point. Its modular, extensible design philosophy means any manufacturer can differentiate on it. And its status as an international standard determines it has the opportunity to support a software ecosystem as vast as Arm and x86.
This judgment received fairly consistent echoes during my visits. The basic view is that RISC-V's greatest contribution to the industry is not creating another "Chinese chip," but dealing everyone a new hand of cards. The moats dug over decades by x86 and Arm appear, for the first time, not insurmountable during the window where AI is rewriting computing paradigms.
But it must be said. Breaking the impossible trinity is an ambition. To turn ambition into victory, the hardest bone must be chewed: high-performance computing.
RISC-V is already firmly seated in the embedded market. But as soon as the benchmark shifts to data centers, servers, and AI computing, the question immediately becomes sharp. This is the thread to follow next.
This Momentum Needs to Build in Mainland China
Globally, RISC-V is not a concept unique to China. Google, Meta, Qualcomm, NVIDIA, and Tesla have embraced RISC-V to varying degrees. The EU, through its Chips Act, has invested tens of billions of euros to support RISC-V R&D. The EuroHPC launched the DARE project, worth approximately €240 million, aiming to gradually replace HPC processors with RISC-V starting from 2025, with "digital sovereignty" written behind it.
For the same RISC-V, China sees supply chain security and cost, while the world sees the next-generation architectural freedom for AI. These two forces happen to converge at this moment.
But to truly build momentum and push the ecosystem from embedded to high-performance, the place with the most dominant energy potential today is Mainland China. This judgment is backed by several thrusts.
First is the "computing power flood" brought by AI. The industry consensus is that by 2030, the global semiconductor market will exceed $1 trillion, with over 70% related to AI. AI's appetite for computing power, memory bandwidth, and chip-to-chip interconnect far exceeds any previous application. The flow of computing power surges toward the high-performance end like a tide. Whoever lacks a sufficient computing base will be left behind.
Of course, there's also supply tightening from export controls. The U.S. Commerce Department has repeatedly tightened export controls on advanced computing chips; NVIDIA itself admits its share in China is almost zero. While the new Vera is coming, none of its price, delivery schedule, or availability are in the hands of Chinese manufacturers. On one side is rising demand, on the other is constrained supply—this scissors gap is precisely where China's ecosystem is most anxious and also most imaginative.
Additionally, there's structural cost reduction from open source. An industry expert specializing in cloud chip selection during my research broke down the data center cost sheet. In high-performance servers, GPU and CPU chips together account for 50% to 80% of hardware costs. Any effort to lower the total cost ultimately lands on the most expensive chip. What's unique about RISC-V is precisely its open-source nature: x86 is a closed-source black box, Arm is a private domain controlled by a single licensor, while RISC-V returns the instruction set as a public good to the entire industry. When a manufacturer doesn't need to pay licensing fees or be choked by the instruction set itself, the cost structure of the CPU industrial chain has a chance to be structurally rewritten.
In Mainland China, on top of these three thrusts lies a layer unique to it, which can be summarized as "central direction-setting, local amplification." The Ministry of Industry and Information Technology this year issued high-quality development special projects related to RISC-V data centers. Local governments followed up with policy funds and application scenarios for hard tech. This combination of top-down and bottom-up synergy is not present in Europe or the U.S.
More telling is the shift in attitude. A few years ago, a leader from among the "six major" domestic CPU manufacturers once mocked those working on RISC-V to their face as "nothing but a motley crew." Today, all six manufacturers have passed national tests, and some are willing to be the first movers, seriously considering grafting their next-generation attempts onto RISC-V. Between "motley crew" and "first mover" lies precisely the process of the past two years where technology, policy, and market forces jointly turned the narrative.
If Europe's embrace of RISC-V is mainly driven by the single goal of "digital sovereignty," then the thrust in Mainland China comes from the superposition of four forces: supply chain security, cost structure, technological sovereignty, and application explosion. This is also why the world's most bustling RISC-V venue, the densest concentration of IP companies, and the fiercest high-performance race are almost all concentrated in Mainland China.
A phrase that has become industry consensus is: RISC-V is China's home ground.
Entry Ticket, Still Just the Entry Ticket
To quantify RISC-V's progress in high-performance computing, the industry tacitly sets a threshold: achieving a SPEC integer (SPECint) score of 15 per GHz.
This threshold needs a brief explanation to avoid misinterpretation. SPEC CPU 2006 and 2017 are long-used industry-standard processor performance benchmarks. The integer score (SPECint) measures a CPU's capability in general integer operations. "Per GHz" means stripping out the influence of clock frequency, purely comparing the execution efficiency of the microarchitecture itself. In other words, this score of 15 competes over how much work a single core can do per unit time without relying on clock boosts—it measures design level, not process benefits.
Why 15? Because the baseline for high-performance CPU microarchitectures in the x86 and Arm camps is roughly around this level. Significantly below this number, a RISC-V core can hardly claim to be "on the same starting line as mature architectures." In other words, 15 points isn't an absolute ceiling but a qualification line. Crossing it means earning the right to enter the high-performance club's conversation; failing to cross means market narratives remain stuck in the embedded and low-to-mid-range space.
An industry expert deeply involved in high-performance microarchitecture design explained the industrial meaning behind this qualification line during my research. The success of Apple's M-series and Arm Neoverse tells everyone that to tear open a seam in a market dominated by a mature architecture like x86 for decades, the only reliance is higher power efficiency. First, establish a foothold in performance per unit, then wait for advanced processes to mature and boost clock speeds. This path also applies to RISC-V.
So, has this line been reached? The answer is: multiple Mainland Chinese teams have reached and even surpassed it consecutively.
On the open-source side, a leading domestic open-source high-performance RISC-V core has achieved a score of 14.78 on a real eight-core mesh network, basically aligning with the previously stated goal of 15.
It's worth mentioning that the team proactively clarified industry bias against open source: open source does not equal low quality. What they want to leave for the industry is a practical, usable open-source baseline. The significance of this baseline is that any small-to-medium chip vendor no longer needs to reinvent the wheel; starting from an open-source core, they can enter the starting line of high-performance. This is a capability neither the x86 black box nor Arm's single licensor can offer.
The commercial IP camp is even more diverse. A rough consensus is that currently, no fewer than five Mainland Chinese vendors have achieved or claimed to achieve scores above 15 for their high-performance RISC-V cores, with some teams even reaching the 16 to 18 range, with typical scenario frequencies exceeding 3.4 GHz.
"Crossing the 3 GHz milestone is truly stepping into the gate of high-performance processors," declared a seasoned architect with considerable force during my interview.
But benchmark scores are just the entry ticket. The real contest lies beyond the scores.
From a Single Core to a Full System: Another Engineering Leap
The most noteworthy change in Mainland China's RISC-V scene over the past year is the shift in focus from a single core to an overall leap towards "computing subsystems."
To understand this, one must first understand what a real server CPU looks like. It's not just an instruction set execution unit; it's an entire SoC comprising dozens of cores, shared caches, memory controllers, I/O channels, security islands, power management units, plus the on-chip interconnect network that organizes it all. The latter is usually called NoC, more precisely, a coherent NoC: it must ensure that dozens or even hundreds of cores see a consistent memory view. It is the central nervous system of large-scale multi-core systems.
How critical is this layer? Intel, AMD, and NVIDIA have their own coherent bus designs; Arm has the CMN series IP; Huawei's Ascend has its own HCCS. Globally, companies capable of commercializing coherent NoC IP are few, each requiring a decade-scale iteration. Without a good coherent NoC, even the strongest single cores are just isolated islands.
And as of today, some Mainland Chinese RISC-V vendors have self-developed commercialized coherent on-chip networks. The basic consensus is that this is a key marker for domestic RISC-V moving from "making cores" to "making systems." An industry practitioner interviewed said that enterprises in Mainland China impacting the RISC-V server chip high ground now number no fewer than ten, a density unthinkable a few years ago.
Beyond NoC, there's a long list of "hard metrics that add zero to benchmark scores but determine whether servers are willing to install it." BMC (Baseboard Management Controller), IPMI (Intelligent Platform Management Interface), virtual media support, full-stack RAS (Reliability, Availability, Serviceability)—these are the most basic requirements for data center operation and maintenance. And there's a very practical yield design called Partial Goods: when a core, a cache segment, or a DDR channel fails on a huge server chip, the entire chip cannot be scrapped; it must be able to mask the bad area and continue shipping in a degraded state. This design directly impacts yield rates, impacting yields means impacting economics.
What best reflects ambition is that a Mainland Chinese vendor has delivered a 40-core RISC-V server processor with fully self-developed IP. The most interesting aspect of this processor is not its scale, but its restraint: zero custom instruction sets, 100% compliant with the RVA23 standard. Behind this lies an almost repeated industrial iron law: in the server market, following rules is more valuable than being flashy.
What is RVA23? A simple explanation: it's the Application Processor Profile finalized by the RISC-V International Foundation in 2024, solidifying a set of core extension instructions into a unified "contract," including 58 mandatory and 23 optional extensions. Any processor claiming RVA23 compliance can theoretically run the same binary software. Its significance to the RISC-V ecosystem is similar to Arm's introduction of Armv8-A: a key step from "a hundred schools of thought contend" towards "a conversational standard."
Zero custom extensions, strict alignment with RVA23—this means the chip gave up the shortcut of "boosting scores" with private instructions and placed its promise on long-term software compatibility. The basic consensus is that this is the most pragmatic posture adjustment in Mainland China's RISC-V charge into the server market over the past few years.
Another set of comparative data beyond benchmarks better illustrates the real slope of RISC-V's upward climb. On typical workloads like video codec, domestic RISC-V high-performance processors have achieved 90% of the performance of contemporary x86 products and 96% of Arm counterparts. In encryption/decryption computing, performance even reached 1.88 times that of x86 and 1.67 times of Arm. For core operators in large model inference, performance is close to 1.67 times the Arm level. Behind these numbers lies a full-stack hardware and software delivery, including operating systems, toolchains, and computing libraries, not an isolated piece of silicon.
More reassuring are chips that have taped out and are already running at client sites. A 64-bit domestic RISC-V processor integrating eight cores has completed mass production tape-out on a 12nm process. Within two weeks of receiving packaged samples, it ran the Ubuntu graphical interface and mainstream desktop applications. Its viable applications are down-to-earth: edge-side large model all-in-one machines, RISC-V native compilation clusters, laptops, cloud terminals, and even automotive are within its range. From being able to benchmark to booting, to installing an OS, to doing work—each step is not short, but each step is being crossed, bit by bit.
The Real Opponent Isn't Arm, It's the Moat Behind Arm
But once we reach this point, another fact must be laid out: the higher RISC-V climbs, the clearer the unavoidable opponent becomes—not the x86 or Arm instruction sets themselves, but the moat dug behind them over decades.
This moat is called ecosystem. And its deepest segment is called CUDA.
A veteran who worked at NVIDIA for many years once poured a bucket of cold water of clarity on peers during my research. She said Jensen Huang himself never considered NVIDIA a chip company; today, the real advantage of GPUs may not be in performance per unit, but in the incredibly powerful CUDA software ecosystem. There are millions of CUDA developers globally, backed by over a decade of cultivated operator libraries, compilation toolchains, debuggers, profilers, and thousands of papers and textbooks around CUDA. What RISC-V must challenge is precisely this mountain.
But interestingly, where Arm and x86 find RISC-V difficult to handle is precisely the fulcrum for RISC-V's counterattack. Bao Yungang from the Institute of Computing Technology, Chinese Academy of Sciences, broke down the opportunity of RISC-V for AI into three layers of logic during our exchange. This framework received fairly broad agreement during my visits.
The first layer is synergy. RISC-V inherently grew from CPU instruction sets; adding AI extensions is a natural step. In the 80s, CPUs added floating-point instructions; in the 90s, multimedia instructions (SIMD); eventually, these all merged into mainstream CPU design. AI extensions merging into CPUs is just history repeating. And in the age of agent AI, workloads requiring repeated calls and decisions between multiple models precisely demand closer synergy between CPUs and accelerators. This is exactly the problem that NVIDIA's Vera, "the first standalone CPU designed for agent AI," aims to solve. If RISC-V can integrate AI extension instructions into the CPU baseline, it gains a head start at the synergy layer.
The second layer is tailoring. The diversity of AI inference scenarios far exceeds training. The cloud needs full-blown large models, the edge needs distilled versions, and the device side needs ultimate power efficiency. x86 and Arm instruction sets are "full sets," not easily trimmed; RISC-V's inherently modular design means every vendor can pick the subset they need from a set of extensions (M integer multiply/divide, A atomic operations, F single-precision float, D double-precision float, V vector, etc.) to create more compact, targeted products.
The third and most critical layer is the software stack. Currently, most domestic AI chip companies operate in vertical silos, each doing its own thing. Software team sizes easily reach hundreds or thousands, with repetitive labor over and over. A number circulating in the industry: in a leading domestic GPU vendor's R&D team of over a thousand, only about two hundred work on chips, while the remaining six to seven hundred work on software. If RISC-V could unify standards at the AI instruction set level, software stacks, compilers, and operator libraries could follow suit. Chip vendors could travel light, returning their focus to microarchitecture and process. This is the path with a chance to truly contend with CUDA.
As for what the underlying AI chip might look like in the future, the industry offers two imaginations. One is called the "Baby RISC-V" approach: stuffing a massive number of small, simple RISC-V cores inside the accelerator, specifically responsible for scheduling data flow and when to use what instructions, dedicating precious silicon area entirely to compute units. Tenstorrent represents this path, and there are Mainland Chinese teams attempting this direction.
The other is "Big RISC-V," using RISC-V as the high-performance main control core, handling scheduling and heavy tasks. The basic view is that the two paths are not mutually exclusive. More likely, Baby and Big will coexist in the same SoC in the future, where underneath, regardless of physical devices, matrix units, or vector engines, a unified software programming interface is accessed via RISC-V. This interface is the root of ecological prosperity.
A bolder vision has already been drawn as an evolution curve: from RISC-V plus AI (simple coupling of CPU and accelerator), to AI plus RISC-V (AI computing dominant, RISC-V control auxiliary), eventually reaching RISC-V equals AI (deep fusion of instruction set and AI computing power, CPU as the foundation for AI computing). Whether this curve holds depends on engineering realization over the next five to ten years, but it at least shows that RISC-V's imagination space for AI is far beyond "making a substitute outside Arm."
The Real Problems Are Plentiful, and All Are Hard
Up to this point, the story seems neatly told. But a responsible industry analysis must lay out the other half: RISC-V's charge into high-performance computing faces plenty of real problems, and all are hard.
The first real problem is incomplete and fragmented ecosystem. Xu Qingwei, Senior Software and Ecosystem Director at Blue Silicon Computing, minced no words in my presence: RISC-V's biggest challenges compared to x86 and Arm are incomplete ecosystem, incomplete specifications, ecosystem fragmentation, plus insufficient software maturity. The root of fragmentation lies in custom instructions; every vendor wants to differentiate with private extensions, ultimately tearing the software ecosystem into isolated islands. The server CPU with "zero custom, full RVA23" mentioned earlier is, in essence, the most pragmatic answer to this real problem: valuing rules over flashiness.
The second real problem hides in toolchains and verification. The EDA link exposes domestic RISC-V's shortcomings particularly clearly. Zhang Chunlin, Technical Director at Synopsys, told me at an industry event that the industry has equipped Arm with very complete compatibility test suites and benchmarks, while RISC-V still lags far behind; plus, various parties customize instructions based on open source, each customization meaning significant verification engineering. There's another difficulty: RISC-V is an open architecture. When code is casually modified today, whether it improves or worsens performance, no one wants to wait until chip tape-out to know the answer. Therefore, hardware-software co-verification must be completed before tape-out.
How hard is verification? A set of publicly available data from the industry: the initial performance error between simulator and RTL for a domestic open-source high-performance core team was as high as 12.4% on SPEC integer and 30.6% on floating-point, meaning simulation predictions and real performance were severely off. Many companies spent great effort on fine-grained calibration to force these errors down to 1.8% and 2.6%. Behind these numbers lies the most unglamorous but grinding work in high-performance processor development—homework no team aspiring to make server CPUs can skip.
Then there are the unavoidable mountains of single-core performance and power efficiency. The industry consensus is that the single-core performance and on-chip interconnect bus performance of current domestic RISC-V chips are still in the catching-up phase. To establish a foothold in data centers, there's much road to travel. The contest of power efficiency is even more subtle; it relies on process, power management, and the most fundamental circuit design—each an area where x86 and Arm camps have built muscles over decades.
Andes Technology Chairman Lin Zhiming gave a very apt analogy: transistors before were like beds sleeping on flat ground; after FinFET, everyone changed to sleeping on 3D vertical beds; looking ahead, it's like building skyscrapers on a single chip, all to squeeze more computing power in limited physical space. In the post-Moore era, whoever builds this building taller and more power-efficient wins. For RISC-V to compete on power efficiency in this building against mature architectures, it doesn't rely on the instruction set itself, but on nearly artisan-level circuit design skill, using custom data paths to painstakingly extract clock speed and power efficiency.
The most practical issue is process and time. Domestic high-end processes indeed still have issues; this is just a transitional state. What if after investing in tape-out today, the channel narrows tomorrow and you can't get the chips back? Each chip vendor has its own calculation. Liu Ya'nan, Chip Technology Director at China Mobile's Cloud Computing Product Department, said something quite candid during my research: the future is bright, and victory is certain, but this process, especially in the data center field, will take longer than everyone expects. This sentence deserves repeated citation because it represents the industry's most sober expectation management for RISC-V's high-performance charge.
Door Opened, Road Remains Long
After circling back, we return to the opening question: When NVIDIA knocks on the door with Vera, is the only viable path for China's self-developed CPUs to "follow Arm's lead"?
All evidence points to the same answer: another track exists, and the home ground of this track is in Mainland China. Several domestic players have already obtained the entry ticket of 15 points; hard data center metrics like coherent NoC, RAS, and Partial Goods are being tackled one by one; a server CPU with zero custom extensions and strict RVA23 alignment has taped out, marking the industry truly growing up according to "server rules"; real orders from scenarios like automotive, communications, and video transcoding are already endorsing RISC-V.
But it must also be acknowledged that a flagship product with head-to-head overall performance against x86 and Arm has not truly emerged, and the ecological moat of CUDA is far from being bridged in a few years. Every step RISC-V climbs upward is accompanied by real problems—fragmentation, EDA shortcomings, single-core power efficiency, process benefits, confidential computing—none solvable overnight by slogans or policy.
Breaking the "impossible trinity" is not a slogan. It means RISC-V must simultaneously piece together autonomy, controllability, and prosperity—each alone is something that takes decades to achieve. The current situation is that the foundation for autonomy has been laid, the engineering for controllability is underway, and the embryo of prosperity is faintly visible. The door has been pushed open, but behind it lies a road longer than anyone expected.
NVIDIA's Vera will enter Chinese clients' ordering systems in August, priced far beyond $20,000 per chip. How many Chinese clients will accept it, how long its supply can be maintained, and at what point the next round of tightened controls might turn it into a "use one, lose one" inventory—these are the industry's immediate worries. RISC-V cannot meet all demand at this August time point, nor does it need to. The question it must answer is not the supply of this particular CPU today, but rather: a decade from now, when the next wave of computing revolution hits again, will China's self-developed CPUs still bet their fate on someone else's table.
Those once called the "motley crew" now hold an entry ticket they've painstakingly pieced together. Whether they can collectively complete those unglamorous, grinding tasks, allowing RISC-V to truly have its place at the high-performance computing table—this is the question most worthy of being repeatedly asked on the track of China's self-developed CPUs over the next five years.
This article is from the WeChat public account: Big Orange Finance , author: Guanwang Finance, original title: "NVIDIA CPU Advances, China's RISC-V Responds – Semiconductor Deep Dive - Part Four"
