There's been major news flooding social media feeds lately: ADI and Empower Semiconductor have announced a definitive agreement under which ADI will acquire Empower in an all-cash transaction valued at $1.5 billion.
Musk once said that in the data-intensive era, ever-increasing power demands pose unprecedented challenges for power supply design. (Anyway, they're running out of transformers to run transformers.)
From Empower's completion of a Series D funding round of over $140 million in September 2025 to its acquisition by ADI just 8 months later, this clearly reminds us that power semiconductors have now become as crucial as GPUs and HBM.
So, what technologies is ADI targeting, and what progress are power supply manufacturers currently making in AI data centers? Today, EEWorld provides an overview of these issues.
Empower, What's Their Background?
Many may not be familiar with Empower; it's a power chip company that received investment from Google. Founded in 2014 by three analog design veterans, they viewed the Integrated Voltage Regulator (IVR) as the "low-hanging fruit" for data centers. This chip addresses the longstanding trade-off between power density and energy efficiency by eliminating or integrating discrete components.
Their solutions are highly favored by Marvell. Last June, Empower Semiconductor announced a deep collaboration with Marvell to jointly develop Integrated Voltage Regulator (IVR) and Vertical Power Delivery (VPD) architectures. The core goal is to upgrade traditional board-level voltage regulation designs to silicon-integrated or near-chip power supply solutions, tackling various power delivery challenges in the kilowatt-class chip era.
This company has four particularly noteworthy technologies:
First, IVR Voltage Regulator
In the data-intensive era, IVR is seen as the future of data centers. Its core value lies in: 1) solving the two major challenges of high path loss and hindered transient response in the AI age; and 2) achieving high power integration through its high-frequency characteristics. It integrates all functional modules of a power supply into a single chip package, ready for plug-and-play, making power design simpler while offering an extremely compact size.
Empower's patented IVR technology is key to enabling Chiplet and system-level power. Traditional PMICs, with their multiple discrete components, suffer from slow speed, high cost, and large size. As data centers approach their energy consumption limits, IVR is designed to replace discrete, bulky PMICs while significantly reducing power loss and improving transient response.
IVR eliminates all independent components, utilizes FinFET processes to achieve switching frequencies in the hundreds of MHz, integrates dozens of discrete components into a single IC, reduces PCB area, enables nanosecond-level transient response, allows the chip to be configured and programmed, and is extremely small, allowing placement anywhere in the system. IVR achieves this by eliminating magnetic components and multilayer ceramic capacitors (MLCCs). Consequently, the entire package volume is 3–5 times smaller than the inductors used in typical power delivery systems.
Second, ECAP Silicon Capacitors
The ECAP silicon capacitor developed by Empower is designed for use alongside IVR or VPD. Its principle is similar to an MLCC, but its ESL is one hundredth or even lower, making it particularly suitable for high-frequency filtering. It optimizes the high-frequency impedance of the PDN, resulting in a more stable and cleaner chip power supply. The dielectric material of silicon capacitors differs from MLCCs, offering more stable capacitance unaffected by voltage or temperature.
ECAPs are manufactured using semiconductor photolithography technology. With picohenry-level equivalent inductance and zero-bias decay characteristics, they provide pure filtering guarantee in the hundred-MHz frequency band. They feature ultra-low Equivalent Series Inductance (ESL) and Equivalent Series Resistance (ESR), enabling broadband performance up to 10 GHz. High capacitance density and ultra-thin profiles allow for chip-side, land-side, or embedded substrate integration in single or multi-domain configurations. These capacitors offer outstanding stability and reliability, with no degradation due to DC/AC bias, aging, or temperature, ensuring stable performance across all operating conditions. They come in both standard portfolios and fully customized designs.
Third, VPD Vertical Power Delivery
Lateral Power Delivery (LPD) is a mature, well-proven technology. However, bound by fundamental physical laws, as processor operating currents continue to climb, power losses caused by resistance and inductance effects within the Power Delivery Network (PDN) intensify. The Vertical Power Delivery (VPD) architecture delivers power vertically through PCB layers directly to the processor above, effectively shortening the electrical transmission distance from VRM to SoC. This results in lower resistive losses, better transient response, improved signal integrity, freed-up space on the front of the motherboard, and enhanced scalability.
Empower's vertical power delivery technology, Crescendo, achieves fast transient response, precise voltage control, and excellent power integrity by placing high-density regulators directly beneath the load. Its scalable, digitally configurable architecture reduces losses, maximizes power density, and eliminates the need for bulky external components or decoupling capacitor banks. Crescendo is designed for demanding xPU and accelerator platforms, enabling higher performance per watt while simplifying system design to support the rapid evolution of next-generation computing.
Fourth, FINFAST Technology
FinFast is Empower's breakthrough power technology platform, built on five foundational pillars: innovative power architecture, FinFET-based power design, advanced power packaging, advanced magnetics, and silicon capacitors. These technologies together enable ultra-high power density, exceptional efficiency, and industry-leading dynamic performance. FinFast is designed for AI, data center, networking, and chipset systems, enabling products that redefine the possibilities of modern power delivery.
The Deeper Meaning Behind ADI's Acquisition
According to analysis by "Third-generation Semiconductor Canteen," ADI has a well-established layout in 48V/800V cabinet and board-level power supplies. However, the last millimeter from outside the chip to directly under the die was a gap. Empower's IVR+ECAP precisely fills this gap, while its vertical power delivery Crescendo platform can handle 3000A+ current with transient response 20 times faster. With the rapid development of large models, Agents, and embodied intelligence, AI accelerator card and system power consumption have quickly risen, with single-system/single-board power delivery pressures entering the kilowatt range. Time is tight and the task is heavy; there's no time to start R&D from scratch. For an analog giant with a market cap approaching $200 billion, $1.5 billion for a ticket into "in-package" power is a very good deal.
A review of the past 18 months shows ADI methodically building its presence in the AI data center field: In April 2024, it established μModule as its main product line for data centers, solving board-level integration; in August 2025, it joined NVIDIA's 800V ecosystem, with data center power business growing 50% year-over-year; at APEC 2025, it launched SiC smart switches, targeting the 800V primary side (PFC/LLC); in February 2026, it defined the "Physical Intelligence" strategy; on March 4, 2026, it developed a new coupled inductor structure called Notch CL (NCL), hinting at Vertical Power Delivery (VPD); on March 27, 2026, it released an 800V white paper, concluding that 800V HVDC is the ultimate endgame; and on May 19, 2026, it acquired Empower for $1.5 billion, filling the final millimeter inside the package.
Currently, very few companies globally can deliver a mass-producible IVR platform, and Vertical Power Delivery (VPD) along with in-package integration is widely recognized as the industry's future. It can be said that Empower's acquisition was almost inevitable.
Development Trends in AI Data Center Power Supplies
Higher integration and vertical power delivery are the direction for AI power supplies. Infineon once shared that future AI power supplies will develop in three phases:
Phase 1 is Discrete/Lateral power delivery. The power stage, inductors, and capacitors are placed directly beside the processor (GPU). This offers the lowest cost and a mature ecosystem and quality system. However, when GPU current exceeds 850–1000A, losses surpass 100W, and total PDN resistance is about 90–140 μΩ.
Phase 2 is Back-side Vertical power delivery (BVM). As the name suggests, the power delivery modules are arranged vertically, penetrating from the backside of the substrate/motherboard to connect directly with the processor, shortening the transmission path. By eliminating spacing between multiple small modules and removing power/control signal routing beneath the processor, power density is increased, motherboard design is simplified, and total PDN resistance is dramatically reduced to 10–15 μΩ (89% lower than lateral).
Phase 3 is Substrate-Integrated Voltage Regulator (SIVR) power delivery. The voltage regulator is directly integrated into the substrate, further streamlining the vertical transmission path, representing the optimal solution for loss control. It can reduce substrate PDN losses by an additional 10–15%, achieving a total PDN resistance of 7–10 μΩ (93% lower than lateral).
From this perspective, IVR is a further optimization of VPD power supplies, while VPD technology is the entry ticket to Phase 3.
IVR: Progress by Other Manufacturers
Currently, there are three IVR implementation schemes: 1) Mounting the IVR on the backside of the motherboard PCB, similar to "standard" vertical power delivery. The process is relatively simple, but PDN resistance is the highest. 2) Installing it near the xPU die. For lower-power systems, the chip is packaged within the package beside the xPU, making installation easier than on the pad side. 3) Embedding the IVR in the substrate. Reducing the IVR's thickness allows it to be embedded directly into the substrate right under the xPU die, resulting in small PDN resistance and high current capacity.
In the IVR field, Empower is not alone. Ferric and Intel have introduced IVR solutions, and Infineon is also closely watching this technology.
American manufacturer Ferric is another collaborator with Marvell. Its IVR can be used in "substrate-embedded" configurations, with 1.2-2V input, 0.25-1.5V output, frequency 60-100MHz, thickness 0.55-1mm, and current density up to 4.5A/mm².
In a previous interview, Ferric stated: "With funding from Intel and the U.S. government, we are developing some key underlying technologies to enable IVR. At the time, we were researching thin-film ferromagnetic materials that could be integrated with semiconductors to miniaturize the entire power converter system, thereby achieving high-density IVR to solve this bottleneck—this is our current progress."
Intel promoted FIVR (Fully Integrated Voltage Regulator) technology years ago. Intel's FIVR integrates the IVR directly inside the CPU, greatly simplifying system design and making the power solution extremely simple. Intel used IVR technology in its 4th generation CPUs, integrating the IVR directly into the CPU, using air-core inductors (ACI), though magnetic inductors (CoaxMIL) were also used in subsequent designs. Efficiency reached up to 90% for 1.8V input and 1V output, with a loop bandwidth of 60MHz. However, Intel later paused this technology for unknown reasons, with thermal dissipation possibly being one factor.
Infineon identified Substrate Voltage Regulator (SVR/SIVR) technology long ago and is researching multiple concepts for standardization. Infineon has also proposed a hybrid control concept.
Silicon Capacitors: The "Industrial Rice" of HPC
Silicon Capacitors (SiCap) were born with a mission—to replace MLCCs in HPC—hence they're also called the "industrial rice" of HPC. Silicon capacitors are a high-density capacitor technology based on semiconductor processes. Utilizing silicon-based materials and microscopic structures like 3D trenches and stacks, they achieve high capacitance density, low ESR, and low ESL, making them suitable for HPC, AI chips, and RF scenarios. Compared to MLCCs, SiCaps use MOS or DRAM stacking processes to integrate capacitors into silicon wafers, resulting in thinner profiles (typically <100μm) and higher density (up to 1.3–2.5 μF/mm²).
Benefiting from explosive demand in AI, data centers, and 5G, the SiCap market continues to expand. In H1 2025, S-SiCap revenue grew 210%, partly driven by CoWoS-S AI chip orders. The global silicon capacitor market was valued at approximately $2–2.25 billion in 2025 and is projected to reach $2.5–3 billion by 2030, with a CAGR of about 4.8–5%. High-density versions (e.g., 3D SiCap) are growing faster: around $202 million in 2024, projected to reach $407 million by 2031; the overall high-density market was $1.1 billion in 2024 and is projected to reach $2.5 billion by 2033.
Murata is a major player in silicon capacitors. Murata's high-density silicon capacitors are developed using semiconductor MOS processes and employ 3D structures to significantly increase electrode surface area, thereby boosting electrostatic capacity within a given footprint. Murata's silicon technology is based on a monolithic structure embedded in an amorphous substrate (single-layer MIM and multi-layer MIM—MIM stands for Metal/Insulator/Metal).
Murata's silicon capacitors share the same DNA as semiconductor MOS processes, featuring full module default models built with proven, consistent data, thus offering predictable, highly reliable performance. Compared to other capacitor technologies, Murata's silicon capacitor technology offers 10x higher reliability, primarily due to oxides formed during high-temperature curing. Additionally, complete electrical testing is performed at the end of the production process, preventing early failures.
Murata uses a special structure called "Tripod Pillar," a "tetrapod" shape, to increase surface area and enhance silicon capacitor electrostatic capacity. Furthermore, utilizing a newly developed Nanoporous structure can increase capacity up to five times. As silicon capacitors can be further miniaturized and thinned, forming a system-level solution with IVR technology, their EC2006P model can provide 36.8μF capacitance within a 4mm x 4mm package.
Samsung Electro-Mechanics is another key player in silicon capacitors. On May 20, Samsung Electro-Mechanics announced signing a two-year contract worth approximately 1.5 trillion won to supply silicon capacitors to a global large enterprise. Samsung Electro-Mechanics plans to expand its supply scope from AI servers to diverse scenarios like autonomous driving, mobile devices, and High-Performance Computing (HPC).
Rohm is also involved in silicon capacitors. Its first-generation product, BTD1RVFL, as a mass-produced surface-mount type, achieved an ultra-small 0402 size (0.4mm×0.2mm). Compared to standard 0603 size (0.6mm×0.3mm) products, mounting area can be reduced by about 55%. For fine patterning, it uses Rohm's proprietary microfabrication technology "RASMIDTM," enabling 1μm-level processing. It incorporates a TVS diode, offering excellent ESD tolerance. By improving package dimensional accuracy, the backside electrode edges (i.e., the contact surface with the circuit board) have been successfully designed closer to the device's periphery.
Domestic players are also focusing on silicon capacitors. Aipu Technology's S-SiCap Gen4 has achieved a capacitance density of 3.8 μF/mm², taking the lead in embedded substrate packaging, with mass production expected to start gradually from 2026. Startups like Langxi Technology and Senmaru Electronics are also rising rapidly. Their 3D silicon capacitor products achieve capacitance density of 1.5 μF/mm², successfully breaking foreign monopolies and finding wide application in markets like AI computing chips and high-speed optical modules.
VPD: Steady Advancement
At this year's CES, NVIDIA confirmed that Rubin will use a VPD solution. According to NVIDIA, the Rubin architecture will feature wider and more numerous HBM4 memory. Since HBM occupies all the space around the GPU package physically, there's no room left for Lateral Power Delivery (LPD), making VPD the definitive solution. Coincidentally, Intel and Google have also begun experimenting with VPD solutions. Even Huawei is paying attention; they have a patent application for a "chip vertical power supply system," aiming to provide a Voltage Regulator Module (VRM) design for chip power supply.
Thus, VPD is set to become one of the most critical technologies for modern processors. Besides Empower, Infineon, Monolithic Power Systems (MPS), Vicor, TDK, and others have also made significant progress in AI data center power supplies.
In March last year, Infineon launched the OptiMOS TDM2454xx four-phase power module, achieving true Vertical Power Delivery (VPD) and offering industry-leading current density of 2 Amps/mm². This module follows Infineon's 2024 launch of the OptiMOS TDM2254xD and TDM2354xD two-phase power modules, continuing to provide excellent power density for accelerated computing platforms.
Infineon states that in traditional horizontal power delivery systems, current must flow across the semiconductor wafer surface, increasing resistance and causing significant power loss. VPD reduces resistive losses by shortening the current transmission path, thereby improving system efficiency.
Utilizing Infineon's robust OptiMOS 6 trench technology power components and embedded chip packaging, the OptiMOS TDM2454xx module offers excellent electrical and thermal performance. Combined with innovative ultra-thin inductor design technology, it continuously pushes the limits of VPD system performance and quality. Furthermore, the module's structural design facilitates modular tiling and improves current conduction, enhancing electrical, thermal, and mechanical performance. The module supports up to 280A current in a four-phase configuration and integrates an embedded capacitor layer within a compact 10x9 mm² package. Paired with Infineon's XDP controller, it enables a stable, durable high-current-density power solution.
MPS (Monolithic Power Systems) is also very active in VPD deployment, with reports indicating MPS has a significant share in H100 GPU power solutions. However, MPS's VPD solution goes by a different name: "Z-axis Power Delivery" (ZPD). Z-axis power delivery places the voltage regulator on the bottom side of the PCB, directly under the processor. This method can significantly reduce PDN losses (by over 10 times).
Last year, MPS launched a new generation of ultra-high power density AI power solutions targeting AI server needs. Its core product, MPC24380, adopts a Z-axis power delivery architecture, integrates output capacitors, and pairs with a top-mounted DrMOS design for optimized heat dissipation. It boasts impressive features like four channels with 260A high output current and ultra-high power density of 2A/mm². MPS also launched the MPC22158 in different specifications, achieving two channels of 130A output current in an ultra-compact volume, helping to power AI chips with advantages like high efficiency and high integration, solving energy and thermal challenges.
Vicor has been involved in VPD development for a long time and is a confirmed partner of NVIDIA. Following NVIDIA's announcement at CES that Rubin would use VPD architecture, Vicor became a major beneficiary, with its stock market activity quite lively. Reports indicate that in 48V AI system applications, Vicor once held up to 85% market share, with partners including NVIDIA, Google, Intel, AMD, Cerebras, and Tesla.
Vicor's VPD solution is an integrated module composed of three layers: the bottom layer is a Gearbox, the middle layer is a VTM current multiplier array, and the top layer is a PRM regulator. Together, these three layers form a complete VPD solution, which Vicor calls DCM (Divided Core Magnetics).
The Gearbox performs two functions: 1) it contains high-frequency decoupling capacitors, and 2) it redistributes current from the VTMs to form a pattern that mirrors the processor above. The size of the VTM array depends on the processor's input current requirements, and the size of the PRM depends on total power demand. If a GPU or ASIC requires multiple power rails, the VTM and PRM layers can be implemented using independent PRMs and VTMs respectively, sized to meet the current and voltage requirements of each specific rail.
Vicor's VPD solution places the MCM/GCM current multiplier directly beneath the processor, further reducing PDN resistance to 5–7 μΩ, maximizing AI processor computing power and energy efficiency. According to Vicor, vertical power delivery can reduce PDN losses by 95%.
TDK is also involved in VPD. Its launched μPOL DC-DC converter utilizes chip embedding technology SESUB to achieve optimal compact size, making it ideal for 1A to 200A vertical power in these applications.
TDK's FS1525 integrates a power inductor to smooth the current ripple generated when the μPOL pushes power into the load. This integration reduces parasitic effects, enabling a smaller form factor and higher efficiency. By compressing all components into a small power module, the DC-DC can deliver a power density of 127 Amps per cubic centimeter.
The module implements a more advanced modulation scheme called Adaptive On-Time (AOT) modulation, achieving ultra-fast transient response and internal loop compensation. Based on a Phase-Locked Loop (PLL), this modulation scheme achieves efficiencies of 91% and 89% at 15 Amps and 25 Amps, respectively. Additionally, I2C and PMBus provide engineers with additional telemetry options.
In Conclusion
Processor and data center architectures are changing to meet the higher voltage demands of servers running AI and Large Language Models (LLMs). Once, servers ran on just a few hundred watts. But over the past decades, the situation has changed dramatically due to the massive increase in data processing needs and user demands for faster processing. NVIDIA's Grace Blackwell chips consume 5 to 6 kilowatts, roughly 10 times the total power consumption of servers in the past.
As AI servers transform and single-board power consumption enters the kilowatt range, whoever can more efficiently squeeze the power supply into the space-starved board, freeing up more space for the more critical computing chips, will win. Technologies like IVR, silicon capacitors, and VDP are undoubtedly key to achieving this breakthrough. ADI's acquisition confirms that AI power supplies urgently need upgrading and transformation. It's believed these technologies will see rapid development in the coming years.
References
[1]ADI:https://www.analog.com/cn/newsroom/press-releases/2026/5-19-2026-adi-to-acquire-empower-semiconductor.html
[2]EETimes:https://www.eetimes.com/adi-to-acquire-empower-to-join-data-centers-power-gold-rush/
[3]ChargerHead:https://mp.weixin.qq.com/s/YLOI9xCpx9xw-XruV7o1aA
[4]Third-generation Semiconductor Canteen:https://mp.weixin.qq.com/s/EcSOlnRwpJvaf1N2pWaFPg
[5]Empower:https://www.empowersemi.com/wp-content/uploads/2026/05/Empower_APM-Brochure_May2026_spreads_digital-opt.pdf
[6]Liu Power:https://mp.weixin.qq.com/s/SqsotkkqBYceV3Ag_n6C7Q
[7]Rohm:https://rohmfs-rohm-com-cn.oss-cn-shanghai.aliyuncs.com/cn/products/databook/white_paper/passive/common/silicon_capacitors_btd1rvfl_wp-c.pdf
This article is from the WeChat public account "EEWorld" (ID: EEworldbbs), author: Fu Bin
