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Microsoft announces plans to build a commercially viable quantum computer by 2029, a significant acceleration from the previous industry consensus of a decade. The breakthrough is fueled by their new Majorana 2 quantum chip, which boasts a record-breaking average qubit lifetime of 20 seconds—a 1,000-fold reliability improvement over its predecessor. This leap was achieved by leveraging topological qubits, a theoretically more stable technology using Majorana zero modes, and switching the core superconducting material from aluminum to lead. Crucially, Microsoft's "Discovery" agentic AI platform accelerated the R&D process. AI agents autonomously analyzed vast experimental data, optimized manufacturing parameters (like the lead alloy composition), and solved issues like "ghost noise," dramatically speeding up experimentation. While the 20-second coherence time is a landmark, challenges remain: scaling from 12 qubits to the millions needed for practical applications, managing compilation costs, and verifying quantum results. Skeptics call for peer-reviewed data, and questions persist about whether even 20 seconds is sufficient for complex algorithms like breaking RSA encryption. The race is on with other approaches (superconducting, trapped ions), but Microsoft's confidence in its topological roadmap signals a potential shortcut to a scalable quantum future.

SemiAnalysis has published a detailed teardown report on the HiSilicon Kirin 9030 Pro chipset found in Huawei's Mate 80 Pro. Fabricated using SMIC's most advanced N+3 node without EUV lithography, the analysis reveals significant technical achievements and strategic shifts. The report indicates SMIC's N+3 has achieved transistor density comparable to TSMC's N6 (113.4 vs 107.7 MTr/mm²), primarily through aggressive use of Self-Aligned Quadruple Patterning (SAQP) for its metal layers. This results in a notably small 32.5nm M0 metal pitch. However, SemiAnalysis notes this achievement comes with significantly higher process complexity, cost, and potential yield challenges compared to competitors using more advanced tools. The Kirin 9030 design maximizes this constrained density. While its GPU performance has improved ~70% and matches Qualcomm's 2022 flagship level, the CPU core's IPC lags behind current top-tier designs from Apple and Qualcomm, a gap attributed to the underlying manufacturing technology rather than design capability. Facing long-term restrictions on advanced tools, Huawei is charting a new path. The report highlights the company's "LogicFolding" roadmap, a 3D stacking technique aimed at shortening signal paths to boost performance and efficiency. The goal is to reach 5GHz frequency and a projected density of 295 MTr/mm² by 2031. SemiAnalysis concludes that export controls have not halted China's chip progress but have fundamentally altered its trajectory, making it more expensive and complex. This has spurred innovation in alternative areas like 3D stacking and domestic EDA tool development, with Huawei's supply chain also beginning to integrate Chinese memory from CXMT.

How Hard Is It to Make a Chip? A Division Error Cost $475 Million Chip expert Shi Kan, a researcher at the Chinese Academy of Sciences and a popular tech creator, explains the immense challenges of chip development. Chips are foundational to modern technology, but their creation is extraordinarily difficult. The journey from sand to a functional chip involves complex design and manufacturing, but a critical bottleneck is verification—ensuring the design works flawlessly before costly production. A single, undetected bug can have catastrophic consequences, as illustrated by the infamous 1994 Intel Pentium FDIV bug. A flaw in the floating-point division unit forced a recall costing $475 million. Unlike software, chips cannot be easily patched after manufacture, making "first-time success" paramount. However, industry surveys show only 24% of chip projects achieve this; over three-quarters require at least one costly re-spin due to design flaws. Verification has thus become the dominant phase, consuming up to 70% of the design cycle. The core challenge is a "verification impossible triangle" between high performance, good debuggability, and low cost. Exhaustively verifying a modern CPU core could take 15,000 years with software simulation, or 30 years with advanced hardware emulation—timeframes utterly impractical for development. Despite being essential, verification is often seen as unglamorous "dirty work," receiving less academic attention than fields like AI. Shi and his team are tackling this by developing an agile verification research framework called ENCORE, based on FPGA technology, to improve verification efficiency and debug capability. Beyond research, Shi engages in public science communication through long-form video content, aiming to demystify chip technology, AI, and computer science. He argues for the value of pursuing "hard and long-term" endeavors, whether in the meticulous world of chip verification or in creating substantive educational content, believing such sustained effort is likely the right path forward.

On June 15, 2026, Li Auto unveiled details of its self-developed chip, Mahe M100, for its new L9 Livis model. CTO Xie Yan stated the goal was not just a faster chip, but a fundamentally different one, targeting the chip architecture itself. While competitors like NIO, Xpeng, and Huawei highlight TOPS (computing power) figures for their self-developed chips, Li Auto’s Mahe M100 focuses on redesigning the underlying architecture. It employs a "dynamic data flow architecture" to address memory bandwidth bottlenecks in large model inference, claiming up to 3x the effective computing power of Nvidia's Thor U for its specific workloads and a 40% reduction in latency. The chip's design was peer-reviewed and accepted at ISCA 2026. However, this performance is highly optimized for Li Auto's own VLA2.1 algorithm, meaning it may not generalize as well to other tasks. Li Auto aims to achieve full-stack in-house development with Mahe M100, covering chip, compiler, OS, AI algorithms, and domain controller—a level of vertical integration few competitors match. Beyond the chip, CEO Li Xiang introduced a new strategic narrative: the "embodied intelligent vehicle," defined as an integration of an EV, a professional driver, an AI computer, and a life assistant. This shifts competition from features like large screens to systemic AI capabilities. A key commitment was that Li Auto's Mahe VLA autonomous driving model will match Tesla's FSD V14 by Q4 2026, with specific OTA milestones set for July, September, and December. Financially, Li Auto faces pressure with declining revenue and vehicle gross margins since Q4 2025, while maintaining high R&D investment (approx. ¥12B in 2026, 50% AI-related). Its 2026 sales target is 550,000 vehicles, up from 406,000 in 2025. The new L9 Livis garnered over 10,000 pre-orders in two weeks. The effectiveness of these strategic moves—new products, OTAs, and the novel chip architecture—will begin to show in Q3 2026 financial results, with the year-end FSD V14 benchmark being the ultimate test.

China's Photonics Industry: Bottlenecks and Breakthroughs In the global AI race, computing chips dominate the narrative, but the underlying bottleneck increasingly defining the scale of AI clusters is light—or more specifically, optical connectivity. Optical modules, which translate electrical signals to light and vice versa, are crucial for connecting thousands of GPUs in AI data centers, preventing data congestion and ensuring efficient model training. High-speed modules (800G, 1.6T) are now standard, with performance hinging on advanced DSP (Digital Signal Processor) chips. This is where a critical dependency lies. Two US giants—Marvell and Broadcom—collectively dominate over 90% of the high-end DSP chip market. Chinese optical module leaders like Zhongji Innolight and Eoptolink rely on these chips to manufacture modules for overseas AI customers, primarily in North America. While this creates a supply chain vulnerability, complete decoupling is difficult. Marvell derives over half its revenue from Greater China, and the US firms depend on Chinese partners for chip packaging and optical components. The risk from laser chips (e.g., from Lumentum), another key component, is considered more manageable due to multiple global suppliers and faster progress in domestic alternatives from companies like YOFC and Accelink. To mitigate risks, China's industry is pursuing a multi-pronged strategy: diversifying supply chains and locking in long-term orders; fostering a domestic market ecosystem to adopt homegrown DSPs from firms like Huawei HiSilicon and CETC; accelerating R&D in high-speed DSPs and advanced packaging; and investing in next-gen technologies like silicon photonics and Co-Packaged Optics (CPO) to reduce reliance on discrete DSPs. The ultimate solution lies not in short-term博弈 but in persistent advancement of domestic high-end chip R&D and manufacturing. While challenges remain in performance, certification, and ecosystem building, China's vast domestic market and manufacturing base provide a crucial buffer, buying time for the industry to achieve greater technological independence.