SemiAnalysis 拆解华为麒麟 9030：制程走不动了，把芯片折叠起来

marsbitPublicado em 2026-06-15Última atualização em 2026-06-15

Resumo

半导体分析机构SemiAnalysis近期发布了对华为麒麟9030芯片的详细拆解报告。该芯片采用中芯国际N+3制程，其最小金属间距（32.5nm）甚至小于英特尔18A制程，逻辑密度也追平了台积电N6水平。然而，这一成果是在没有EUV光刻机的情况下，通过复杂的四重图案化等工艺实现的，导致制造成本更高、工艺更复杂且良率控制难度大。 在芯片设计上，华为海思在近乎相同的芯片面积内，通过增加CPU核心、GPU单元和NPU核心，并扩大缓存，显著提升了麒麟9030的性能。其GPU性能已追平2022年旗舰水平，但受限于制造工艺，CPU性能与当前使用先进制程的苹果、高通旗舰芯片仍有明显差距。 面对制程进步的瓶颈，华为提出了转向“时间域”优化的τ缩放定律和“LogicFolding”（逻辑折叠）技术路线图。该技术旨在通过3D堆叠将同一逻辑模块拆分为上下两层，以缩短信号路径、提升频率并降低功耗。华为的目标是到2031年将大核频率提升至5GHz，并将等效密度推向台积电14A级别。不过，分析指出，其密度计算方式与传统方法不同，且实现难度极高。 报告总结认为，出口管制虽未阻止中国芯片进步，但改变了其发展路径，使其代价更高。同时，中芯国际的先进制程技术正扩散至华虹等公司，国产EDA工具和存储芯片（如长鑫）也在供应链中取得进展。未来的关键在于，华为的3D堆叠路线能否在成本可控下，使中国芯片在关键应用场景达到“够用”水平，从而重塑供应链价值。

撰文:潮向研究

半导体逆向工程领域,TechInsights 统治了几十年。上周末,Dylan Patel 的 SemiAnalysis 正式发布了旗下 STEEL 实验室(Teardown Engineering & Evaluation Lab)的第一份公开拆解报告,对象直指全球最受关注的芯片之一,华为 Mate 80 Pro 搭载的麒麟 9030 Pro,采用中芯国际最先进的 N+3 制程。

时机耐人寻味。TechInsights 正在被私募股权出售,而 SemiAnalysis 的营收已经超过了这家老牌巨头。Dylan 选择在这个节点亮剑,用的是一份技术含量极高的拆解报告,配合俄勒冈州实验室的实拍芯片照片。

报告的标题就是一枚炸弹:SMIC N+3 的最小金属间距(M0 pitch)仅 32.5nm,比 Intel 最新 Panther Lake 处理器使用的 18A 制程的 36nm 还小。

中芯国际在没有 EUV 光刻机的情况下,金属间距做到了比 Intel 还细?

这条消息如果只看标题,足以让整个半导体圈炸锅,但 SemiAnalysis 自己在报告第二段就泼了冷水,这是一个"cherry picked metric",一个被刻意挑选的指标。

本文将为你解读这份拆解报告,

密度追平,代价高昂

SMIC 的 N+3 制程在晶体管密度上,确实追平了台积电的 N6。

STEEL 实验室通过 TEM(透射电子显微镜)截面分析,测量出 N+3 的 Bohr 密度为 113.4 MTr/mm2,略高于台积电 N6 的 107.7 MTr/mm2。单元高度从 N+2 的 252nm 缩减到 228nm,接触栅极间距(CGP)从 63nm 缩减到 57nm。这些数字放在一起,意味着 SMIC 在没有 EUV 的条件下,通过纯 DUV 光刻,把逻辑密度做到了台积电成熟 7nm 级别。

代价是什么?

SMIC 的 M0 层使用的是自对准四重图案化(SAQP),即把一张光罩的图案经过四次加工来实现更精细的线条。台积电 N6 在同一层只需要双重图案化(SADP)。四重意味着更多的光罩数量、更高的套刻精度要求、更复杂的工艺流程,以及更高的成本。

SemiAnalysis 在截面图中直接看到了 SAQP 的代价:N+3 的 M0 沟槽呈现明显的倒梯形轮廓(底部比顶部窄),沟槽底部有清晰的阻挡层富集带。这种形貌虽然有助于铜填充,但在 32.5nm 这个间距上,工艺控制的难度急剧上升。

用一个交易员能听懂的比喻:SMIC 在做同样面额的钞票,但每张的印刷成本是台积电的数倍,而且良率风险更大。密度一样,经济学完全不同。

麒麟 9030:在受限条件下,把每一寸硅片都榨干

华为海思的芯片设计能力是另一个维度的故事。

从芯片面积看,麒麟 9030 和上一代 9020 几乎一样大(约 140mm2),但内部塞进了更多的东西:CPU 从 1 个大核 +3 个中核升级到 1 大 +4 中,GPU 计算单元从 4 个增加到 6 个,NPU 也多了一个 Tiny 核心,各级缓存全线扩容。N+3 的密度提升让华为在同样的芯片尺寸里装下了更多逻辑单元。

性能上,STEEL 实验室引用了公开跑分数据,给出的定位很清晰:麒麟 9030 的 GPU 性能(Maleoon 935)大致追平了 2022 年的旗舰级别,3DMark WLE 跑分比上一代提升 70%,略超骁龙 8+ Gen 1,但与当前旗舰骁龙 8 Elite Gen 5 相比,差距在 2.4 到 2.6 倍。

CPU 的情况更能说明问题。大核 TaiShan Prime 的每时钟性能(IPC)大致处于 Arm Cortex-X2 水平,一个 2021 年的设计。苹果 2020 年发布的 M1 Firestorm 核心,IPC 仍然高出 35%。最新的 Apple M5 P 核心,IPC 高出 60%,绝对性能是 2.7 倍。

差距的根源不在设计,在制程。苹果和高通用的是台积电 N4、N3P,这些制程在电压-频率曲线上有本质优势:同样面积可以塞进更多晶体管,同样功耗可以跑更高频率。华为的核心设计水平对标的是行业一线的上一代,但被困在了两代以前的制造工艺里。

当制程走不动了,华为准备“折叠”

报告最具前瞻价值的部分,是华为在 2026 年 ISCAS 会议上公布的τ缩放定律和 LogicFolding 路线图。

传统的半导体缩放在二维平面上推进:把晶体管做小,把金属线做细。摩尔定律走了几十年,本质就是在干这件事。华为现在提出的τ缩放,把优化目标从空间域转移到了时间域,核心是缩短数据移动和处理的时间成本,包括晶体管开关延迟、信号传播延迟、计算和存储的延迟。

LogicFolding 是这套理论的工程实现。简单说,就是把同一个逻辑模块拆成上下两层,面对面堆叠,通过超精细间距的混合键合连接。这样做的直接好处是缩短了最长的信号路径。现代芯片里,很大一部分功耗和延迟花在了驱动长连线和中继缓冲器上。把逻辑垂直折叠后,关键路径变短,频率可以上去,功耗可以下来。

华为给出了一条激进的路线图:麒麟 9030 的大核频率是 2.75GHz,实验室里已经跑通 3.39GHz 的样片,目标是 2031 年达到 5GHz,同时通过 3D 堆叠将等效密度推到 295 MTr/mm2,对标台积电 14A 级别。

SemiAnalysis 对此保持警惕。他们指出,华为的密度计算方式和传统代工厂不同:3D 堆叠的密度是按封装面积算的,把多层有源逻辑叠在一起,自然会得到更高的数字。如果用同样的方法去算 AMD 的 MI450X(N2 顶层+N3P 底层),理论密度高达 460.2 MTr/mm2,远超华为 2031 年的目标。

但方向本身值得重视。华为走这条路,本质上是在制程受限的前提下,把"代工厂的活揽到了系统设计公司身上。AMD 的 V-Cache 在缓存上做 3D 堆叠,AMD MI350X 把 IO 和互联挪到底层芯片,华为要做的更彻底,直接把同一个逻辑块拆开,垂直分布,这在工程难度上是另一个量级的挑战。

出口管制重塑了竞赛的维度

SemiAnalysis 最后的结论直截了当:出口管制没有阻止中国的芯片进步,但改变了进步的路径和代价。

SMIC 的 N+3 证明,不用 EUV 也能做到 N6 级别的逻辑密度。但这条路的成本更高,工艺更复杂,良率更难控制。往下走,每一步的边际难度都在加大:更多的光罩、更严格的套刻精度、更昂贵的多重图案化。理论上 N+4 可以做到 137.8 MTr/mm2(对标台积电 N5),N+5 如果加入背面供电,甚至可以接近 Intel 18A 的 HP 库。但每一步都比上一步更难、更贵、容错空间更小。

与此同时,SMIC 的 N+2 和 N+3 制程正在向华虹转移,阿里平头哥、寒武纪等设计公司也可能成为受益者。芯片制造知识从单一代工厂向生态系统扩散,这让针对单一企业的制裁效力进一步稀释。

而在设计端,华为和北京大学已经在为 LogicFolding 开发国产 EDA 工具原型。这不等于替代了 Synopsys 和 Cadence 的完整工具链,但国产 EDA 正在朝着"架构-制程-封装协同优化"的方向演进。

一个有意思的细节:STEEL 在拆解中发现,麒麟 9030 Pro 的 DRAM 来自三星(K4L2E165YD, LPDDR5X-9600, 1a 工艺节点),而 16GB 的 Pro Max 版本同时出现了三星和长鑫存储(CXMT)的封装。长鑫的芯片封装日期标注为 2025 年第 45 周,制程密度与业界 1z 级别相当。这意味着中国存储芯片已经开始进入华为旗舰供应链,尽管制程仍落后于三星和 SK 海力士一到两代。

对投资者而言,真正值得跟踪的信号在于华为的 3D 堆叠路线能不能在成本可控的前提下,让中国产芯片在手机、AI 推理、网络设备等场景中达到够用的门槛。

一旦够用成立,这条供应链的战略价值就会被重新定价。

Perguntas relacionadas

QSemiAnalysis 关于麒麟 9030 采用的 SMIC N+3 制程，其金属间距（M0 pitch）报告的核心内容是什么？

A报告的核心内容是：SMIC N+3 制程的最小金属间距（M0 pitch）达到了 32.5nm，比英特尔最新 18A 制程的 36nm 还小。但报告同时指出，这是一个被刻意挑选的指标。虽然这一技术细节显示出中芯国际在 DUV 光刻下取得的惊人突破，但它是通过复杂的四重图案化（SAQP）技术实现的，这带来了更高的工艺难度、光罩数量和成本，其经济学和成熟度与英特尔或台积电的先进制程完全不同。

Q华为麒麟 9030 芯片在性能上与当前行业旗舰芯片（如骁龙、苹果芯片）相比，主要差距体现在哪里？其根源是什么？

A麒麟 9030 在 GPU 性能上大致追平了 2022 年的旗舰水平，但与当前旗舰（如骁龙 8 Elite Gen 5）仍有 2.4 到 2.6 倍的差距。CPU 方面，其大核的每时钟性能（IPC）约相当于 2021 年的 Arm Cortex-X2 水平，远落后于苹果 M5 等最新核心。报告指出，差距的根源主要在于制造工艺。华为受限于使用中芯国际的 N+3 制程，而苹果和高通使用的是台积电更先进的 N4、N3P 等制程。后者在晶体管密度、电压-频率曲线和功耗效率上拥有本质优势，使得同样设计水平的核心能实现更高的绝对性能。

Q华为提出的“LogicFolding”（逻辑折叠）技术是什么？其目标是什么？

A“LogicFolding”是华为提出的一种 3D 堆叠技术，旨在当平面制程微缩（摩尔定律）遇到瓶颈时，从时间维度（τ缩放）提升芯片性能。其核心思想是将同一个逻辑模块拆分成上下两层，通过超精细间距的混合键合进行面对面的垂直堆叠。这样做能大幅缩短芯片内部最长的信号路径，从而有望在同等或更低的功耗下提升运行频率。华为的目标是，通过 3D 堆叠将等效逻辑密度提升至 295 MTr/mm²（对标台积电 14A 级别），并计划在 2031 年实现其大核频率达到 5GHz。

Q文章认为出口管制对中国半导体产业产生了什么具体影响？

A文章认为，出口管制（如限制获取 EUV 光刻机）并未阻止中国芯片技术的进步，但深刻地改变了其进步路径并大幅提高了代价。具体体现在：1. 技术路径上：迫使中芯国际等企业在没有 EUV 的情况下，依赖更复杂、成本更高的多重图案化（如 SAQP）等 DUV 技术来追赶先进制程密度，导致每一步工艺提升都更困难、更昂贵。2. 产业扩散上：中芯国际的先进制程技术（如 N+2/N+3）正在向华虹等国内其他代工厂转移，芯片设计知识也在向更多公司扩散，这削弱了针对单一企业制裁的效果。3. 创新方向上：促使华为等系统设计公司转向 3D 堆叠（如 LogicFolding）和架构-制程-封装协同优化等非传统路径，以在制造受限的情况下寻求性能突破。

Q从麒麟 9030 Pro 的拆解中，能看到中国半导体供应链哪些方面的进展？

A从拆解中可以看到中国半导体供应链在多个关键领域的进展：1. 逻辑制造：中芯国际 N+3 制程在逻辑密度上已达到台积电 N6 水平，证明了在受限条件下实现技术追赶的能力。2. 存储芯片：长鑫存储（CXMT）的 LPDDR5X 内存芯片已进入华为 Mate 80 Pro Max 版本的供应链，与三星产品混用，其制程密度达到业界 1z 级别，显示中国存储芯片已能用于旗舰产品，尽管制程仍落后国际领先水平一到两代。3. 设计工具：华为与北京大学已在为 3D 堆叠技术开发国产 EDA 工具原型，表明在关键软件工具上的自主化努力。4. 生态扩散：先进制造知识在国内代工厂间转移，更多芯片设计公司（如平头哥、寒武纪）可能受益，供应链韧性在增强。

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On June 15, Chinese AI company Zhipu's stock surged up to 47.6% in Hong Kong, closing with a 32.82% gain. This sharp rise followed two key industry events. On June 12, Anthropic was compelled by a U.S. government export control order to suspend global access to its latest flagship models, Claude Fable 5 and Claude Mythos 5, impacting developers and businesses reliant on them. The next day, Zhipu announced it was opening access to its new open-source flagship model, GLM-5.2, for all Coding Plan users, with API and model weights (under the MIT license) to follow. The Anthropic incident highlighted a critical shift in the AI industry: beyond raw capability, the stability, continuous accessibility, and control over AI models are becoming equally vital, especially as AI integrates deeper into business workflows. Zhipu's move, emphasizing that "frontier intelligence should not belong to a few nor be subject to arbitrary revocation," positioned its open, accessible model as an alternative. GLM-5.2 focuses on "Long Horizon Tasks" with a 1M context window, aiming for consistency in complex, extended projects. Market analysts suggest this event exposes the risk of dependency on closed-source models subject to single jurisdiction policies, potentially accelerating a shift toward domestic base models and localized deployments. The investment response indicates a new valuation metric is emerging—prioritizing which companies can provide AI capabilities that are not only advanced but also reliably and sustainably accessible.

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After the U.S. Banned Fable 5, Zhipu's Stock Soared 47%

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