Analyst: Changes in HBM Packaging Route, SPHBM4 May Push AI Chip Bottlenecks to Base Chips

06/23 03:55

On June 23, analyst Damnang stated in an article published on June 22 that the newly released SPHBM4 standard by JEDEC does not make DRAM itself faster, larger, or cheaper, but changes the way HBM connects with GPUs. Traditional HBM4 requires a silicon interposer to connect to the GPU, while SPHBM4 attempts to bypass the silicon interposer and connect HBM directly to the organic packaging substrate. The core technology of SPHBM4 is the reuse of HBM4's DRAM stacking, redesigning only the bottom base die. Traditional HBM4 has 2048 data signal pins and relies on the silicon interposer to handle extremely dense connection spacing; SPHBM4 reduces the number of pins to 512 and increases the single-pin speed fourfold through 4:1 serialization, theoretically maintaining a bandwidth close to that of HBM4. Damnang believes that the key to this standard is not 'cheap HBM,' but rather the release of advanced packaging capacity. While HBM is indeed expensive and scarce, the silicon interposer and CoWoS are also significant bottlenecks in AI accelerator shipments. If HBM no longer occupies interposer area, the same interposer wafer capacity could support more packaging shipments. The article estimates that in high-end AI accelerators, the silicon interposer area occupied by HBM could be close to half. If this area is removed, the number of packages supported by a single wafer could theoretically increase by 1.5 to 2 times. However, the actual effect still depends on adoption rates, yield, product configurations, and remaining interposer area on the GPU side. Therefore, what SPHBM4 truly releases is capacity, not the cost of a single chip. Even if similar technologies can save 22% to 40% in packaging costs, when considered in the total cost of an AI accelerator, it only accounts for a single-digit percentage. More importantly, once the shipping bottleneck is opened, the output of GPUs and ASICs may increase. The beneficiaries may not be immediately obvious. In the short term, even if a cloud provider or chip company adopts SPHBM4 first, the released CoWoS capacity may be reallocated by TSMC to queued customers, with NVIDIA likely being the most capable of absorbing the additional capacity. For cloud providers developing their own ASICs, the value of SPHBM4 leans more towards the long term: reducing reliance on large silicon interposers and increasing design and shipping flexibility. The value in the supply chain will also shift accordingly. Damnang states that SPHBM4 will shift the technical burden from substrates and silicon interposers to high-speed logic design of the base die. As single-pin speeds increase, PHY, SerDes, clock recovery, equalization, and error correction circuits will become more important. The focus of HBM competition may shift from 'who can stack higher' to 'who can optimize base logic better.' At the company level, Samsung has a vertical integration advantage due to its capabilities in storage, advanced logic processes, and packaging; SK Hynix and Micron rely more on TSMC's advanced nodes to achieve complex base dies; TSMC, even facing reduced interposer area, still masters CoWoS and base die foundry; Intel, with its EMIB, high-speed interconnect, and advanced packaging capabilities, becomes a potential variable. However, SPHBM4 is currently still in the 'standard release, waiting for adoption' stage. The next steps will involve observing three things: which memory manufacturer will be the first to launch SPHBM4 products, whether large cloud providers will incorporate this design into their self-developed ASICs, and whether JEDEC will disclose complete technical details. Damnang is an analyst who has long focused on semiconductors and AI infrastructure, with his Substack primarily publishing analyses of the semiconductor, memory, advanced packaging, wafer foundry, and AI chip supply chains, characterized by breaking down complex engineering issues into industry logic that investors can understand.

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